HyperBus_simulation.vhd


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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.NUMERIC_STD.ALL;

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entity HyperBus_simulation is

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end HyperBus_simulation;

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architecture Behavioral of HyperBus_simulation is

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component s27kl0641 is port(

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    DQ7: inout std_logic;

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    DQ6: inout std_logic;

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    DQ5: inout std_logic;

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    DQ4: inout std_logic;

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    DQ3: inout std_logic;

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    DQ2: inout std_logic;

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    DQ1: inout std_logic;

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    DQ0: inout std_logic;

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    RWDS: inout std_logic;

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    CSNeg: in std_logic;

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    CK: in std_logic;

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    RESETNeg: in std_logic);

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end component;

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signal nReset: std_logic:='1';

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signal nCS: std_logic:='1';

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signal CK: std_logic:='0';

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signal RWDS: std_logic:='Z';

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signal DQ: std_logic_vector(7 downto 0):=x"00";

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begin

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RAM: s27kl0641 port map(

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    DQ7 => DQ(7),

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    DQ6 => DQ(6),

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    DQ5 => DQ(5),

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    DQ4 => DQ(4),

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    DQ3 => DQ(3),

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    DQ2 => DQ(2),

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    DQ1 => DQ(1),

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    DQ0 => DQ(0),

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    RWDS => RWDS,

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    CSNeg => nCS,

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    CK => CK,

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    RESETNeg => nReset);

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process begin

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  RWDS <= 'Z';

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  DQ <= x"00";

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  wait for 200 us;

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  nReset <= '0';

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  wait for 400 ns;

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  nReset <= '1';

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  wait for 1 us;

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  -- WRITE

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  nCS <= '0';

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  wait for 10.1 ns;

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  DQ <= x"20";

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  wait for 2.4 ns;

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  CK <= '1';

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  wait for 2.6 ns;

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  DQ <= x"00";

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  wait for 2.4 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 2.6 ns;

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  DQ <= x"01";

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  wait for 2.4 ns;

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  CK <= '0';

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  wait for 2.6 ns;

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  DQ <= x"00";

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  wait for 2.4 ns;

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  CK <= '1';

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  wait for 2.6 ns;

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  DQ <= x"01";

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  wait for 2.4 ns;

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  CK <= '0';

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  wait for 2.6 ns;

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  DQ <= x"00";

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  wait for 2.4 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 2.5 ns;

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  RWDS <= '0';

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  wait for 2.5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 2.6 ns;

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  DQ <= x"01";

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  wait for 2.4 ns;

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  CK <= '1';

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  wait for 2.6 ns;

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  DQ <= x"a0";

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  wait for 2.4 ns;

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  CK <= '0';

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  wait for 2.6 ns;

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  DQ <= x"00";

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  RWDS <= 'Z';

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  nCS <= '1';

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  wait for 1 us;

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  -- READ

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  nCS <= '0';

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  wait for 10.1 ns;

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  DQ <= x"A0";

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  wait for 2.4 ns;

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  CK <= '1';

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  wait for 2.6 ns;

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  DQ <= x"00";

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  wait for 2.4 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 2.6 ns;

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  DQ <= x"01";

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  wait for 2.4 ns;

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  CK <= '0';

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  wait for 2.6 ns;

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  DQ <= x"00";

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  wait for 2.4 ns;

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  CK <= '1';

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  wait for 2.6 ns;

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  DQ <= x"01";

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  wait for 2.4 ns;

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  CK <= '0';

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  wait for 2.6 ns;

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  DQ <= x"00";

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  wait for 2.4 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  DQ <= "ZZZZZZZZ";

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  CK <= '0';

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  wait for 5 ns;

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  CK <= '1';

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  wait for 5 ns;

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  CK <= '0';

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  wait for 2.6 ns;

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  nCS <= '1';

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  wait for 2.4 ns;

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  DQ <= x"00";

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  wait;

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end process;

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end Behavioral;