1 | /*--------------------------------------------------------------------------
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2 | CH559.H
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3 | Header file for CH559 microcontrollers.
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4 | ****************************************
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5 | ** Copyright (C) W.ch 1999-2014 **
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6 | ** Web: http://wch.cn **
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7 | ****************************************
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8 | --------------------------------------------------------------------------*/
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9 |
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10 | #ifndef _CH559_IAR_H_
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11 | #define _CH559_IAR_H_
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12 |
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13 | #pragma language=save
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14 | #pragma language=extended
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15 |
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16 | #define SFR __sfr __no_init volatile
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17 | //#define XSFR __xdata __no_init volatile
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18 |
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19 | /* Core Registers */
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20 | SFR unsigned char SP @ 0x81; // Stack Pointer
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21 | SFR unsigned char DPL @ 0x82; // Data Pointer Low byte, LSB of DPTR
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22 | SFR unsigned char DPH @ 0x83; // Data Pointer High byte, MSB of DPTR
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23 |
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24 | SFR union
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25 | {
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26 | unsigned char PSW; // program status word
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27 | struct
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28 | {
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29 | unsigned char P : 1; // ReadOnly: parity flag
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30 | unsigned char F1 : 1; // bit addressable general purpose flag 1
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31 | unsigned char OV : 1; // overflow flag
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32 | unsigned char RS0 : 1; // register R0-R7 bank selection low bit
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33 | unsigned char RS1 : 1; // register R0-R7 bank selection high bit
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34 | unsigned char F0 : 1; // bit addressable general purpose flag 0
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35 | unsigned char AC : 1; // auxiliary carry flag
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36 | unsigned char CY : 1; // carry flag
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37 | } PSW_bit;
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38 | } @ 0xD0;
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39 | #define MASK_PSW_RS 0x18 // bit mask of register R0-R7 bank selection
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40 | #define P (PSW_bit.P) // to be src compatible with keils sbit
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41 | #define F1 (PSW_bit.F1)
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42 | #define OV (PSW_bit.OV)
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43 | #define RS0 (PSW_bit.RS0)
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44 | #define RS1 (PSW_bit.RS1)
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45 | #define F0 (PSW_bit.F0)
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46 | #define AC (PSW_bit.AC)
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47 | #define CY (PSW_bit.CY)
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48 |
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49 | SFR union
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50 | {
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51 | unsigned char ACC; // Accumulator
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52 | struct
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53 | {
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54 | unsigned char ACC0 : 1;
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55 | unsigned char ACC1 : 1;
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56 | unsigned char ACC2 : 1;
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57 | unsigned char ACC3 : 1;
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58 | unsigned char ACC4 : 1;
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59 | unsigned char ACC5 : 1;
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60 | unsigned char ACC6 : 1;
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61 | unsigned char ACC7 : 1;
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62 | } ACC_bit;
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63 | } @ 0xE0;
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64 |
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65 | SFR union
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66 | {
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67 | unsigned char B; // B Register
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68 | struct
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69 | {
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70 | unsigned char B0 : 1;
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71 | unsigned char B1 : 1;
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72 | unsigned char B2 : 1;
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73 | unsigned char B3 : 1;
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74 | unsigned char B4 : 1;
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75 | unsigned char B5 : 1;
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76 | unsigned char B6 : 1;
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77 | unsigned char B7 : 1;
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78 | } B_bit;
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79 | } @ 0xF0;
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80 |
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81 | SFR unsigned char SP @ 0x81; // Stack Pointer
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82 | SFR unsigned char DPL @ 0x82; // Data Pointer Low byte, LSB of DPTR
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83 | SFR unsigned char DPH @ 0x83; // Data Pointer High byte, MSB of DPTR
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84 | SFR unsigned char SAFE_MOD @ 0xA1; // WriteOnly: writing safe mode
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85 | SFR unsigned char CHIP_ID @ 0xA1; // ReadOnly: reading chip ID
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86 | // #define CHIP_ID SAFE_MOD
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87 |
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88 | SFR unsigned char GLOBAL_CFG @ 0xB1; // global config, Write@SafeMode
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89 | #define bBOOT_LOAD 0x20 // ReadOnly: boot loader status for discriminating BootLoader or Application: set 1 by power on reset, clear 0 by software reset
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90 | #define bSW_RESET 0x10 // software reset bit, auto clear by hardware
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91 | #define bCODE_WE 0x08 // enable flash-ROM (include code & data area) being program or erasing: 0=writing protect, 1=enable program and erase
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92 | #define bDATA_WE 0x04 // enable Data-Flash (flash-ROM data area) being program or erasing: 0=writing protect, 1=enable program and erase
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93 | #define bXIR_XSFR 0x02 // force MOVX_@R0/@R1 only for xSFR area: 0=MOVX_@R0/@R1 for standard xdata area inclde xRAM&xBUS&xSFR, 1=MOVX_@R0/@R1 for xSFR only
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94 | #define bWDOG_EN 0x01 // enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow
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95 |
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96 | /* Clock and Sleep and Power Registers */
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97 | SFR unsigned char PCON @ 0x87; // power control and reset flag
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98 | #define SMOD 0x80 // baud rate selection for UART0 mode 1/2/3: 0=slow(Fsys/128 @mode2, TF1/32 @mode1/3, no effect for TF2),
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99 | // 1=fast(Fsys/32 @mode2, TF1/16 @mode1/3, no effect for TF2)
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100 | #define bRST_FLAG1 0x20 // ReadOnly: recent reset flag high bit
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101 | #define bRST_FLAG0 0x10 // ReadOnly: recent reset flag low bit
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102 | #define MASK_RST_FLAG 0x30 // ReadOnly: bit mask of recent reset flag
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103 | #define RST_FLAG_SW 0x00 // 00 - software reset, by bSW_RESET=1 @(bBOOT_LOAD=0 or bWDOG_EN=1)
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104 | #define RST_FLAG_POR 0x10 // 01 - power on reset
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105 | #define RST_FLAG_WDOG 0x20 // 10 - watch-dog timer overflow reset
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106 | #define RST_FLAG_PIN 0x30 // 11 - external input manual reset by RST pin
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107 | #define GF1 0x08 // general purpose flag bit 1
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108 | #define GF0 0x04 // general purpose flag bit 0
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109 | #define PD 0x02 // power-down enable bit, auto clear by wake-up hardware
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110 |
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111 | SFR unsigned char PLL_CFG @ 0xB2; // PLL clock config: lower 5 bits for PLL clock Fpll, upper 3 bits for USB 4x clock Fusb4x, Write@SafeMode
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112 | #define MASK_PLL_MULT 0x1F // bit mask of PLL clock Fpll multiple
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113 | #define MASK_USB_4X_DIV 0xE0 // bit mask of USB 4x clock Fusb4x divisor, value 000b means 1000b
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114 |
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115 | SFR unsigned char CLOCK_CFG @ 0xB3; // system clock config: lower 5 bits for system clock Fsys, Write@SafeMode
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116 | #define bOSC_EN_INT 0x80 // internal oscillator enable and original clock selection: 1=enable & select internal clock, 0=disable & select external clock
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117 | #define bOSC_EN_XT 0x40 // external oscillator enable, need quartz crystal or ceramic resonator between X1 and X2 pins
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118 | #define bWDOG_IF_TO 0x20 // ReadOnly: watch-dog timer overflow interrupt flag, cleared by reload watch-dog count or auto cleared when MCU enter interrupt routine
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119 | #define MASK_SYS_CK_DIV 0x1F // bit mask of system clock Fsys divisor, value 00000b means 100000b
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120 | /*
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121 | Fxt = 4MHz~20MHz, from external oscillator @XI&XO
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122 | Fosc = bOSC_EN_INT ? 12MHz : Fxt
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123 | Fpll = Fosc * ( PLL_CFG & MASK_PLL_MULT ) => 288MHz (24MHz~350MHz)
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124 | Kusb = ( PLL_CFG & MASK_USB_4X_DIV ) >> 5
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125 | Fusb4x = Fpll / ( Kusb ? Kusb : 8 ) => 48MHz (Fixed)
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126 | Ksys = CLOCK_CFG & MASK_SYS_CK_DIV
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127 | Fsys = Fpll / ( Ksys ? Ksys : 32 ) => 12MHz (1MHz~56MHz)
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128 | */
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129 | SFR unsigned char SLEEP_CTRL @ 0xEA; // sleep control, Write@SafeMode
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130 | #define bSLP_OFF_USB 0x80 // clock off for USB
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131 | #define bSLP_OFF_ADC 0x40 // clock off for ADC
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132 | #define bSLP_OFF_UART1 0x20 // clock off for UART1
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133 | #define bSLP_OFF_P1S1 0x10 // clock off for PWM1 / SPI1
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134 | #define bSLP_OFF_SPI0 0x08 // clock off for SPI0
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135 | #define bSLP_OFF_TMR3 0x04 // clock off for timer3
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136 | #define bSLP_OFF_LED 0x02 // clock off for LED
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137 | #define bSLP_OFF_XRAM 0x01 // clock off for xRAM
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138 |
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139 | SFR unsigned char WAKE_CTRL @ 0xEB; // wake-up control, Write@SafeMode
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140 | #define bWAK_BY_USB 0x80 // enable wake-up by USB event
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141 | #define bWAK_RXD1_LO 0x40 // enable wake-up by RXD1 low level
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142 | #define bWAK_P1_5_LO 0x20 // enable wake-up by pin P1.5 low level
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143 | #define bWAK_P1_4_LO 0x10 // enable wake-up by pin P1.4 low level
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144 | #define bWAK_P0_3_LO 0x08 // enable wake-up by pin P0.3 low level
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145 | #define bWAK_CAP3_LO 0x04 // enable wake-up by CAP3 low level
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146 | #define bWAK_P3_2E_3L 0x02 // enable wake-up by pin P3.2 (INT0) edge or pin P3.3 (INT1) low level
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147 | #define bWAK_RXD0_LO 0x01 // enable wake-up by RXD0 low level
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148 |
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149 | SFR unsigned char RESET_KEEP @ 0xFE; // value keeper during reset
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150 | SFR unsigned char WDOG_COUNT @ 0xFF; // watch-dog count, count by clock frequency Fsys/262144
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151 |
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152 | /* Interrupt Registers */
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153 | SFR union
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154 | {
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155 | unsigned char IE; // interrupt enable
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156 | struct
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157 | {
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158 | unsigned char EX0 :1; // enable external interrupt INT0 or LED interrupt
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159 | unsigned char ET0 :1; // enable timer0 interrupt
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160 | unsigned char EX1 :1; // enable external interrupt INT1
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161 | unsigned char ET1 :1; // enable timer1 interrupt
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162 | unsigned char ES :1; // enable UART0 interrupt
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163 | unsigned char ET2 :1; // enable timer2 interrupt
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164 | unsigned char E_DIS:1; // disable global interrupts, intend to inhibit interrupt during some flash-ROM operation: 0=enable if EA=1, 1=disable
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165 | unsigned char EA :1; // enable global interrupts: 0=disable, 1=enable if E_DIS=0
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166 | }IE_bit;
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167 | }@ 0xA8;
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168 | #define EX0 (IE_bit.EX0) // to be src compatible with keils sbit
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169 | #define ET0 (IE_bit.ET0)
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170 | #define EX1 (IE_bit.EX1)
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171 | #define ET1 (IE_bit.ET1)
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172 | #define ES (IE_bit.ES)
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173 | #define ET2 (IE_bit.ET2)
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174 | #define E_DIS (IE_bit.EDIS)
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175 | #define EA (IE_bit.EA)
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176 |
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177 | SFR union
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178 | {
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179 | unsigned char IP; // interrupt priority and current priority
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180 | struct
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181 | {
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182 | unsigned char PX0 : 1; // external interrupt INT0 priority level
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183 | unsigned char PT0 : 1; // timer0 interrupt priority level
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184 | unsigned char PX1 : 1; // external interrupt INT1 priority level
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185 | unsigned char PT1 : 1; // timer1 interrupt priority level
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186 | unsigned char PS : 1; // UART0 interrupt priority level
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187 | unsigned char PT2 : 1; // timer2 interrupt priority level
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188 | unsigned char PL_FLAG : 1; // ReadOnly: low level priority action flag
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189 | unsigned char PH_FLAG : 1; // ReadOnly: high level priority action flag
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190 | }IP_bit;
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191 | }@ 0xB8;
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192 | // PH_FLAG & PL_FLAG: current interrupt priority
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193 | // 00 - no interrupt now
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194 | // 01 - low level priority interrupt action now
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195 | // 10 - high level priority interrupt action now
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196 | // 11 - unknown error
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197 | #define PX0 (IP_bit.PX0) // to be src compatible with keils sbit
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198 | #define PT0 (IP_bit.PT0)
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199 | #define PX1 (IP_bit.PX1)
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200 | #define PT1 (IP_bit.PT1)
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201 | #define PS (IP_bit.PS)
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202 | #define PT2 (IP_bit.PT2)
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203 | #define PL_FLAG (IP_bit.PL_FLAG)
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204 | #define PH_FLAG (IP_bit.PH_FLAG)
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205 |
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206 | SFR union
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207 | {
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208 | unsigned char IE_EX; // extend interrupt enable
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209 | struct
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210 | {
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211 | unsigned char IE_SPI0 : 1; // enable SPI0 interrupt
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212 | unsigned char IE_TMR3 : 1; // enable timer3 interrupt
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213 | unsigned char IE_USB : 1; // enable USB interrupt
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214 | unsigned char IE_ADC : 1; // enable ADC interrupt
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215 | unsigned char IE_UART1 : 1; // enable UART1 interrupt
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216 | unsigned char IE_PWM1 : 1; // enable PWM1 interrupt
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217 | unsigned char IE_GPIO : 1; // enable GPIO input interrupt
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218 | unsigned char IE_WDOG : 1; // enable watch-dog timer interrupt
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219 | }IE_EX_bit;
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220 | }@ 0xE8;
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221 |
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222 | #define IE_SPI0 (IE_EX_bit.IE_SPI0) // to be src compatible with keils sbit
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223 | #define IE_TMR3 (IE_EX_bit.IE_TMR3)
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224 | #define IE_USB (IE_EX_bit.IE_USB)
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225 | #define IE_ADC (IE_EX_bit.IE_ADC)
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226 | #define IE_UART1 (IE_EX_bit.IE_UART1)
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227 | #define IE_PWM1 (IE_EX_bit.IE_PWM1)
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228 | #define IE_GPIO (IE_EX_bit.IE_GPIO)
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229 | #define IE_WDOG (IE_EX.IE_WDOG)
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230 |
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231 | SFR unsigned char IP_EX @ 0xE9; // extend interrupt priority
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232 | #define bIP_LEVEL 0x80 // ReadOnly: current interrupt nested level: 0=no interrupt or two levels, 1=one level
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233 | #define bIP_GPIO 0x40 // GPIO input interrupt priority level
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234 | #define bIP_PWM1 0x20 // PWM1 interrupt priority level
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235 | #define bIP_UART1 0x10 // UART1 interrupt priority level
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236 | #define bIP_ADC 0x08 // ADC interrupt priority level
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237 | #define bIP_USB 0x04 // USB interrupt priority level
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238 | #define bIP_TMR3 0x02 // timer3 interrupt priority level
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239 | #define bIP_SPI0 0x01 // SPI0 interrupt priority level
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240 |
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241 | SFR unsigned char GPIO_IE @ 0xCF; // GPIO interrupt enable
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242 | #define bIE_IO_EDGE 0x80 // enable GPIO edge interrupt: 0=low/high level, 1=falling/rising edge
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243 | #define bIE_RXD1_LO 0x40 // enable interrupt by RXD1 low level / falling edge
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244 | #define bIE_P5_5_HI 0x20 // enable interrupt by pin P5.5 high level / rising edge
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245 | #define bIE_P1_4_LO 0x10 // enable interrupt by pin P1.4 low level / falling edge
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246 | #define bIE_P0_3_LO 0x08 // enable interrupt by pin P0.3 low level / falling edge
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247 | #define bIE_P5_7_HI 0x04 // enable interrupt by pin P5.7 (RST) high level / rising edge
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248 | #define bIE_P4_1_LO 0x02 // enable interrupt by pin P4.1 low level / falling edge
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249 | #define bIE_RXD0_LO 0x01 // enable interrupt by RXD0 low level / falling edge
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250 |
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251 | /* FlashROM and Data-Flash Registers */
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252 | SFR unsigned int ROM_ADDR @ 0x84; // address for flash-ROM, little-endian
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253 | SFR unsigned char ROM_ADDR_L @ 0x84; // address low byte for flash-ROM
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254 | SFR unsigned char ROM_ADDR_H @ 0x85; // address high byte for flash-ROM
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255 | SFR unsigned int ROM_DATA @ 0x8E; // data for flash-ROM writing, little-endian
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256 | SFR unsigned char ROM_DATA_L @ 0x8E; // data low byte for flash-ROM writing
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257 | SFR unsigned char ROM_DATA_H @ 0x8F; // data high byte for flash-ROM writing
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258 | SFR unsigned char ROM_CTRL @ 0x86; // WriteOnly: flash-ROM control
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259 | #define ROM_CMD_PROG 0x9A // WriteOnly: flash-ROM word program operation command, for changing some ROM bit of a word from 1 to 0
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260 | #define ROM_CMD_ERASE 0xA6 // WriteOnly: flash-ROM sector erase operation command, for changing all ROM bit of 1KBytes from 0 to 1
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261 | SFR unsigned char ROM_STATUS @ 0x86; // ReadOnly: flash-ROM status
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262 | // #define ROM_STATUS ROM_CTRL
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263 | #define bROM_ADDR_OK 0x40 // ReadOnly: flash-ROM operation address valid flag, can be reviewed before or after operation: 0=invalid parameter, 1=address valid
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264 | #define bROM_CMD_ERR 0x02 // ReadOnly: flash-ROM operation command error flag: 0=command accepted, 1=unknown command
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265 | #define bROM_CMD_TOUT 0x01 // ReadOnly: flash-ROM operation result: 0=success, 1=operation time out
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266 |
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267 | /* Port Registers */
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268 | SFR union
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269 | {
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270 | unsigned char P0; // port 0 input & output
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271 | struct
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272 | {
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273 | unsigned char P0_0 : 1;
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274 | unsigned char P0_1 : 1;
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275 | unsigned char P0_2 : 1;
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276 | unsigned char P0_3 : 1;
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277 | unsigned char P0_4 : 1;
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278 | unsigned char P0_5 : 1;
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279 | unsigned char P0_6 : 1;
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280 | unsigned char P0_7 : 1;
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281 | }P0_bit;
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282 | }@ 0x80;
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283 | #define UDTR (P0_bit.P0_0) // DTR output for UART1
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284 | #define URTS (P0_bit.P0_1) // RTS output for UART1
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285 | #define RXD_ (P0_bit.P0_2) // alternate pin for RXD of UART0
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286 | #define TXD_ (P0_bit.P0_3) // alternate pin for TXD of UART0
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287 | #define UCTS (P0_bit.P0_4) // CTS input for UART1
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288 | #define UDSR (P0_bit.P0_5) // DSR input for UART1
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289 | #define URI (P0_bit.P0_6) // RI input for UART1
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290 | #define UDCD (P0_bit.P0_7) // DCD input for UART1
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291 |
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292 | SFR unsigned char P0_DIR @ 0xC4; // port 0 direction
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293 | #define bUDCD 0x80 // DCD input for UART1
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294 | #define bURI 0x40 // RI input for UART1
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295 | #define bUDSR 0x20 // DSR input for UART1
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296 | #define bUCTS 0x10 // CTS input for UART1
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297 | #define bTXD_ 0x08 // alternate pin for TXD of UART0
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298 | #define bRXD_ 0x04 // alternate pin for RXD of UART0
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299 | #define bURTS 0x02 // RTS output for UART1
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300 | #define bUDTR 0x01 // DTR output for UART1
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301 |
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302 | SFR unsigned char P0_PU @ 0xC5; // port 0 pullup enable
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303 |
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304 | SFR union
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305 | {
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306 | unsigned char P1; // port 1 input & output, not 5VT
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307 | struct
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308 | {
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309 | unsigned char P1_0 : 1;
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310 | unsigned char P1_1 : 1;
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311 | unsigned char P1_2 : 1;
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312 | unsigned char P1_3 : 1;
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313 | unsigned char P1_4 : 1;
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314 | unsigned char P1_5 : 1;
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315 | unsigned char P1_6 : 1;
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316 | unsigned char P1_7 : 1;
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317 | }P1_bit;
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318 | }@0x90;
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319 | #define AIN0 (P1_bit.P1_0)
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320 | #define AIN1 (P1_bit.P1_1)
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321 | #define AIN2 (P1_bit.P1_2)
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322 | #define AIN3 (P1_bit.P1_3)
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323 | #define AIN4 (P1_bit.P1_4)
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324 | #define AIN5 (P1_bit.P1_5)
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325 | #define AIN6 (P1_bit.P1_6)
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326 | #define AIN7 (P1_bit.P1_7)
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327 |
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328 | #define T2 (P1_bit.P1_0) // external count input, not 5VT
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329 | #define T2EX (P1_bit.P1_1) // external trigger input for timer2 reload & capture, not 5VT
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330 | #define PWM3 (P1_bit.P1_2) // PWM output for timer3, not 5VT
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331 | #define SCS (P1_bit.P1_4) // slave chip-selection input for SPI0, not 5VT
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332 | #define MOSI (P1_bit.P1_5) // master serial data output or slave serial data input for SPI0, not 5VT
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333 | #define MISO (P1_bit.P1_6) // master serial data input or slave serial data output for SPI0, not 5VT
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334 | #define SCK (P1_bit.P1_7) // serial clock for SPI0, not 5VT
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335 |
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336 | #define CAP1 (P1_bit.P1_0) // capture1 input for timer2, not 5VT
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337 | #define CAP2 (P1_bit.P1_1) // capture2 input for timer2, not 5VT
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338 | #define CAP3 (P1_bit.P1_2) // capture input for timer3, not 5VT
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339 |
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340 | SFR unsigned char P1_IE @ 0xB9; // port 1 input enable
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341 | #define bSCK 0x80 // serial clock for SPI0
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342 | #define bMISO 0x40 // master serial data input or slave serial data output for SPI0
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343 | #define bMOSI 0x20 // master serial data output or slave serial data input for SPI0
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344 | #define bSCS 0x10 // slave chip-selection input for SPI0
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345 | #define bPWM3 0x04 // PWM output for timer3
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346 | #define bCAP3 0x04 // capture input for timer3
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347 | #define bT2EX 0x02 // external trigger input for timer2 reload & capture
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348 | #define bCAP2 0x02 // capture2 input for timer2
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349 | #define bT2 0x01 // external count input or clock output for timer2
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350 | #define bCAP1 0x01 // capture1 input for timer2
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351 |
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352 | SFR unsigned char P1_DIR @ 0xBA; // port 1 direction
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353 | SFR unsigned char P1_PU @ 0xBB; // port 1 pullup enable
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354 |
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355 | SFR union
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356 | {
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357 | unsigned char P2; // port 2 input & output
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358 | struct
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359 | {
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360 | unsigned char P2_0 : 1;
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361 | unsigned char P2_1 : 1;
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362 | unsigned char P2_2 : 1;
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363 | unsigned char P2_3 : 1;
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364 | unsigned char P2_4 : 1;
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365 | unsigned char P2_5 : 1;
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366 | unsigned char P2_6 : 1;
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367 | unsigned char P2_7 : 1;
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368 | }P2_bits;
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369 | }@ 0xA0;
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370 |
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371 | #define MOSI1 (P2_bit.P2_1) // master serial data output for SPI1
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372 | #define MISO1 (P2_bit.P2_2) // master serial data input for SPI1
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373 | #define SCK1 (P2_bit.P2_3) // serial clock output for SPI1
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374 | #define PWM1 (P2_bit.P2_4) // PWM output for PWM1
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375 | #define T2EX_ (P2_bit.P2_5) // alternate pin for T2EX
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376 | #define RXD1 (P2_bit.P2_6) // RXD input for UART1
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377 | #define TXD1 (P2_bit.P2_7) // TXD output for UART1
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378 |
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379 | #define DA7 (P2_bit.P2_7) // address 7 output for direct low address mode
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380 |
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381 | #define TNOW (P2_bit.P2_5) // tx now output for UART1, indicate transmitting
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382 | #define PWM2 (P2_bit.P2_5) // second PWM output for PWM1
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383 | #define CAP2_ (P2_bit.P2_5) // alternate pin for CAP2
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384 |
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385 | SFR unsigned char P2_DIR @ 0xBC; // port 2 direction
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386 | #define bTXD1 0x80 // TXD output for UART1
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387 | #define bDA7 0x80 // address 7 output for direct low address mode
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388 | #define bRXD1 0x40 // RXD input for UART1
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389 | #define bTNOW 0x20 // tx now output for UART1, indicate transmitting
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390 | #define bPWM2 0x20 // second PWM output for PWM1
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391 | #define bT2EX_ 0x20 // alternate pin for T2EX
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392 | #define bCAP2_ 0x20 // alternate pin for CAP2
|
393 | #define bPWM1 0x10 // PWM output for PWM1
|
394 | #define bSCK1 0x08 // serial clock output for SPI1
|
395 | #define bMISO1 0x04 // master serial data input for SPI1
|
396 | #define bMOSI1 0x02 // master serial data output for SPI1
|
397 |
|
398 | SFR unsigned char P2_PU @ 0xBD; // port 2 pullup enable
|
399 | SFR union
|
400 | {
|
401 | unsigned char P3; // port 3 input & output
|
402 | struct
|
403 | {
|
404 | unsigned char P3_0 : 1;
|
405 | unsigned char P3_1 : 1;
|
406 | unsigned char P3_2 : 1;
|
407 | unsigned char P3_3 : 1;
|
408 | unsigned char P3_4 : 1;
|
409 | unsigned char P3_5 : 1;
|
410 | unsigned char P3_6 : 1;
|
411 | unsigned char P3_7 : 1;
|
412 | }P3_bit;
|
413 | }@ 0xB0;
|
414 |
|
415 | #define RXD (P3_bit.P3_0) // RXD input for UART0
|
416 | #define TXD (P3_bit.P3_1) // TXD output for UART0
|
417 | #define INT0 (P3_bit.P3_2) // external interrupt 0 input
|
418 | #define INT1 (P3_bit.P3_3) // external interrupt 1 input
|
419 | #define T0 (P3_bit.P3_4) // external count input for timer0
|
420 | #define T1 (P3_bit.P3_5) // external count input for timer1
|
421 | #define WR (P3_bit.P3_6) // xdata or xBUS write strobe output
|
422 | #define RD (P3_bit.P3_7) // xdata or xBUS read strobe output
|
423 |
|
424 | #define LED0 (P3_bit.P3_2) // LED0 data output
|
425 | #define LED1 (P3_bit.P3_3) // LED1 data output
|
426 | #define LEDC (P3_bit.P3_4) // LEDC clock output for LED
|
427 | #define XCS0 (P3_bit.P3_4) // xBUS chip-selection 0# output, for address range 0x4000~0x7FFF
|
428 | #define DA6 (P3_bit.P3_5) // address 6 output for direct low address mode
|
429 |
|
430 | SFR unsigned char P3_DIR @ 0xBE; // port 3 direction
|
431 | #define bRD 0x80 // xdata or xBUS read strobe output
|
432 | #define bWR 0x40 // xdata or xBUS write strobe output
|
433 | #define bDA6 0x20 // address 6 output for direct low address mode
|
434 | #define bT1 0x20 // external count input for timer1
|
435 | #define bLEDC 0x10 // LEDC clock output for LED
|
436 | #define bXCS0 0x10 // xBUS chip-selection 0# output, for address range 0x4000~0x7FFF
|
437 | #define bT0 0x10 // external count input for timer0
|
438 | #define bLED1 0x08 // LED1 data output
|
439 | #define bINT1 0x08 // external interrupt 1 input
|
440 | #define bLED0 0x04 // LED0 data output
|
441 | #define bINT0 0x04 // external interrupt 0 input
|
442 | #define bTXD 0x02 // TXD output for UART0
|
443 | #define bRXD 0x01 // RXD input for UART0
|
444 | SFR unsigned char P3_PU @ 0xBF; // port 3 pullup enable
|
445 |
|
446 | SFR union
|
447 | {
|
448 | unsigned char P4_OUT; // port 4 output
|
449 | struct
|
450 | {
|
451 | unsigned char P4_0 : 1;
|
452 | unsigned char P4_1 : 1;
|
453 | unsigned char P4_2 : 1;
|
454 | unsigned char P4_3 : 1;
|
455 | unsigned char P4_4 : 1;
|
456 | unsigned char P4_5 : 1;
|
457 | unsigned char P4_6 : 1;
|
458 | unsigned char P4_7 : 1;
|
459 | }P4_OUT_bit;
|
460 | }@ 0xC0;
|
461 |
|
462 |
|
463 | #define LED2 (P4_OUT_bit.P4_0) // LED2 data output
|
464 | #define LED3 (P4_OUT_bit.P4_4) // LED3 data output
|
465 |
|
466 | #define RXD1_ (P4_OUT_bit.P4_0) // alternate pin for RXD1
|
467 | #define PWM3_ (P4_OUT_bit.P4_2) // alternate pin for PWM3
|
468 | #define CAP3_ (P4_OUT_bit.P4_2) // alternate pin for CAP3
|
469 | #define PWM1_ (P4_OUT_bit.P4_3) // alternate pin for PWM1
|
470 |
|
471 | #define TNOW_ (P4_OUT_bit.P4_4) // alternate pin for TNOW
|
472 | #define TXD1_ (P4_OUT_bit.P4_4) // alternate pin for TXD1
|
473 | #define PWM2_ (P4_OUT_bit.P4_5) // alternate pin for PWM2
|
474 | #define SCS_ (P4_OUT_bit.P4_6) // alternate pin for SCS
|
475 | #define SCK_ (P4_OUT_bit.P4_7) // alternate pin for SCK
|
476 |
|
477 |
|
478 | SFR unsigned char P4_IN @ 0xC1; // ReadOnly: port 4 input
|
479 | #define bSCK_ 0x80 // alternate pin for SCK, not 5VT
|
480 | #define bSCS_ 0x40 // alternate pin for SCS, not 5VT
|
481 | #define bPWM2_ 0x20 // alternate pin for PWM2
|
482 | #define bLED3 0x10 // LED3 data output
|
483 | #define bTNOW_ 0x10 // alternate pin for TNOW
|
484 | #define bTXD1_ 0x10 // alternate pin for TXD1
|
485 | #define bPWM1_ 0x08 // alternate pin for PWM1
|
486 | #define bPWM3_ 0x04 // alternate pin for PWM3
|
487 | #define bCAP3_ 0x04 // alternate pin for CAP3
|
488 | #define bLED2 0x01 // LED2 data output
|
489 | #define bRXD1_ 0x01 // alternate pin for RXD1
|
490 |
|
491 | SFR unsigned char P4_DIR @ 0xC2; // port 4 direction
|
492 | SFR unsigned char P4_PU @ 0xC3; // port 4 pullup enable
|
493 |
|
494 | SFR unsigned char P5_IN @ 0xC7; // ReadOnly: port 5 input
|
495 | #define bRST 0x80 // ReadOnly: pin RST input, not 5VT
|
496 | #define bIO_INT_ACT 0x40 // ReadOnly: GPIO interrupt request action status
|
497 | #define bHP 0x20 // ReadOnly: pin HP input
|
498 | #define bHM 0x10 // ReadOnly: pin HM input
|
499 | #define bDP 0x02 // ReadOnly: pin DP input
|
500 | #define bDM 0x01 // ReadOnly: pin DM input
|
501 |
|
502 | SFR unsigned char P4_CFG @ 0xC7; // port 4 config
|
503 | //#define P4_CFG P5_IN
|
504 | #define bSPI0_PIN_X 0x08 // SPI0 SCS/SCK alternate pin enable: 0=SCS/SCK on P1.4/P1.7, 1=SCS/SCK on P4.6/P4.7
|
505 | #define bP4_DRV 0x04 // P4 driving capability: 0=5mA, 1=20mA
|
506 |
|
507 | SFR unsigned char PORT_CFG @ 0xC6; // port 0/1/2/3 config
|
508 | #define bP3_DRV 0x80 // P3 driving capability: 0=5mA, 1=20mA
|
509 | #define bP2_DRV 0x40 // P2 driving capability: 0=5mA, 1=20mA
|
510 | #define bP1_DRV 0x20 // P1 driving capability: 0=5mA, 1=10mA
|
511 | #define bP0_DRV 0x10 // P0 driving capability: 0=5mA, 1=20mA
|
512 | #define bP3_OC 0x08 // P3 open-drain output enable: 0=push-pull output, 1=open-drain output
|
513 | #define bP2_OC 0x04 // P2 open-drain output enable: 0=push-pull output, 1=open-drain output
|
514 | #define bP1_OC 0x02 // P1 open-drain output enable: 0=push-pull output, 1=open-drain output
|
515 | #define bP0_OC 0x01 // P0 open-drain output enable: 0=push-pull output, 1=open-drain output
|
516 | // bPn_OC & Pn_DIR & Pn_PU: pin input & output configuration for Pn (n=0/1/2/3)
|
517 | // 0 0 0: input only, without pullup resistance
|
518 | // 0 0 1: input only, with pullup resistance
|
519 | // 0 1 x: push-pull output, strong driving high level and low level
|
520 | // 1 0 0: open-drain output without pullup, support input
|
521 | // 1 1 0: open-drain output without pullup, support input, just driving high level strongly for 2 clocks if turning output level from low to high
|
522 | // 1 0 1: quasi-bidirectional (simulated 8051 mode), open-drain output with pullup resistance
|
523 | // 1 1 1: quasi-bidirectional (standard 8051 mode), open-drain output with pullup resistance, just driving high level strongly for 2 clocks if turning output level from low to high
|
524 |
|
525 | SFR unsigned char PIN_FUNC @ 0xCE; // pin function selection
|
526 | #define bPWM1_PIN_X 0x80 // PWM1/PWM2 alternate pin enable: 0=PWM1/PWM2 on P2.4/P2.5, 1=PWM1/PWM2 on P4.3/P4.5
|
527 | #define bTMR3_PIN_X 0x40 // PWM3/CAP3 alternate pin enable: 0=PWM3/CAP3 on P1.2, 1=PWM3/CAP3 on P4.2
|
528 | #define bT2EX_PIN_X 0x20 // T2EX/CAP2 alternate pin enable: 0=T2EX/CAP2 on P1.1, 1=T2EX/CAP2 on P2.5
|
529 | #define bUART0_PIN_X 0x10 // UART0 alternate pin enable: 0=RXD0/TXD0 on P3.0/P3.1, 1=RXD0/TXD0 on P0.2/P0.3
|
530 | #define bXBUS_EN 0x08 // xBUS function enable: 0=disable, 1=enable port 0 used as data bus and P3.6/P3.7 used as bus writing/reading strobe during accessing xBUS
|
531 | #define bXBUS_CS_OE 0x04 // xBUS chip-selection output enable: 0=disable output,
|
532 | // 1=output CS0 (chip-selection 0#, low action) at P3.4, output inversion of address_15 (be equal to CS1, low action) at P3.3 if ALE disabled
|
533 | #define bXBUS_AH_OE 0x02 // xBUS high address output enable: 0=disable output, 1=output address_8~15 at P2.0~P2.7 during accessing xBUS by MOVX_@DPTR instruction
|
534 | #define bXBUS_AL_OE 0x01 // xBUS low address output enable: 0=multiplex low address and data bus during accessing xBUS, 1=output address_0~7 at P4.0~P4.5 & P3.5 & P2.7 directly
|
535 |
|
536 | SFR unsigned char XBUS_AUX @ 0xA2; // xBUS auxiliary setting
|
537 | #define bUART0_TX 0x80 // ReadOnly: indicate UART0 transmittal status
|
538 | #define bUART0_RX 0x40 // ReadOnly: indicate UART0 receiving status
|
539 | #define bSAFE_MOD_ACT 0x20 // ReadOnly: safe mode action status
|
540 | #define bALE_CLK_EN 0x10 // enable ALE output 1/12 Fsys clock during non xBUS operation
|
541 | #define GF2 0x08 // general purpose flag bit 2
|
542 | #define bDPTR_AUTO_INC 0x04 // enable DPTR auto increase if finished MOVX_@DPTR instruction
|
543 | #define DPS 0x01 // dual DPTR selection: 0=DPTR0 selected, 1=DPTR1 selected
|
544 |
|
545 | SFR unsigned char XBUS_SPEED @ 0xFD; // xBUS speed config
|
546 | #define bXBUS1_SETUP 0x80 // xBUS chip-selection 1# setup time: 0=2 clocks, 1=3 clocks
|
547 | #define bXBUS1_HOLD 0x40 // xBUS chip-selection 1# hold time: 0=1 clocks, 1=2 clocks
|
548 | #define bXBUS1_WIDTH1 0x20 // xBUS chip-selection 1# access pulse width high bit
|
549 | #define bXBUS1_WIDTH0 0x10 // xBUS chip-selection 1# access pulse width low bit
|
550 | #define MASK_XBUS1_WIDTH 0x30 // bit mask of xBUS chip-selection 1# access pulse width
|
551 | // bXBUSn_WIDTH1 & bXBUSn_WIDTH0: read or write pulse width for xBUS chip-selection n# peripheral
|
552 | // 00: 2 clocks
|
553 | // 01: 4 clocks
|
554 | // 10: 8 clocks
|
555 | // 11: 16 clocks
|
556 | #define bXBUS0_SETUP 0x08 // xBUS chip-selection 0# setup time: 0=2 clocks, 1=3 clocks
|
557 | #define bXBUS0_HOLD 0x04 // xBUS chip-selection 0# hold time: 0=1 clocks, 1=2 clocks
|
558 | #define bXBUS0_WIDTH1 0x02 // xBUS chip-selection 0# access pulse width high bit
|
559 | #define bXBUS0_WIDTH0 0x01 // xBUS chip-selection 0# access pulse width low bit
|
560 | #define MASK_XBUS0_WIDTH 0x03 // bit mask of xBUS chip-selection 0# access pulse width
|
561 |
|
562 | /* Timer0/1 Registers */
|
563 | SFR union
|
564 | {
|
565 | unsigned char TCON; // timer 0/1 control and external interrupt control
|
566 | struct
|
567 | {
|
568 | unsigned char IT0 : 1; // INT0 interrupt type: 0=low level action, 1=falling edge action
|
569 | unsigned char IE0 : 1; // INT0 interrupt flag, auto cleared when MCU enter interrupt routine
|
570 | unsigned char IT1 : 1; // INT1 interrupt type: 0=low level action, 1=falling edge action
|
571 | unsigned char IE1 : 1; // INT1 interrupt flag, auto cleared when MCU enter interrupt routine
|
572 | unsigned char TR0 : 1; // timer0 run enable
|
573 | unsigned char TF0 : 1; // timer0 overflow & interrupt flag, auto cleared when MCU enter interrupt routine
|
574 | unsigned char TR1 : 1; // timer1 run enable
|
575 | unsigned char TF1 : 1; // timer1 overflow & interrupt flag, auto cleared when MCU enter interrupt routine
|
576 | }TCON_bit;
|
577 | }@ 0x88;
|
578 | #define IT0 (TCON_bit.IT0)
|
579 | #define IE0 (TCON_bit.IE0)
|
580 | #define IT1 (TCON_bit.IT1)
|
581 | #define IE1 (TCON_bit.IE1)
|
582 | #define TR0 (TCON_bit.TR0)
|
583 | #define TF0 (TCON_bit.TF0)
|
584 | #define TR1 (TCON_bit.TR1)
|
585 | #define TF1 (TCON_bit.TF1)
|
586 |
|
587 | SFR unsigned char TMOD @ 0x89; // timer 0/1 mode
|
588 | #define bT1_GATE 0x80 // gate control of timer1: 0=timer1 run enable while TR1=1, 1=timer1 run enable while P3.3 (INT1) pin is high and TR1=1
|
589 | #define bT1_CT 0x40 // counter or timer mode selection for timer1: 0=timer, use internal clock, 1=counter, use P3.5 (T1) pin falling edge as clock
|
590 | #define bT1_M1 0x20 // timer1 mode high bit
|
591 | #define bT1_M0 0x10 // timer1 mode low bit
|
592 | #define MASK_T1_MOD 0x30 // bit mask of timer1 mode
|
593 | #define bT0_GATE 0x08 // gate control of timer0: 0=timer0 run enable while TR0=1, 1=timer0 run enable while P3.2 (INT0) pin is high and TR0=1
|
594 | #define bT0_CT 0x04 // counter or timer mode selection for timer0: 0=timer, use internal clock, 1=counter, use P3.4 (T0) pin falling edge as clock
|
595 | #define bT0_M1 0x02 // timer0 mode high bit
|
596 | #define bT0_M0 0x01 // timer0 mode low bit
|
597 | #define MASK_T0_MOD 0x03 // bit mask of timer0 mode
|
598 | // bT1_M1 & bT1_M0: timer1 mode
|
599 | // 00: mode 0, 13-bit timer or counter by cascaded TH1 and lower 5 bits of TL1, the upper 3 bits of TL1 are ignored
|
600 | // 01: mode 1, 16-bit timer or counter by cascaded TH1 and TL1
|
601 | // 10: mode 2, TL1 operates as 8-bit timer or counter, and TH1 provide initial value for TL1 auto-reload
|
602 | // 11: mode 3, stop timer1
|
603 |
|
604 | // bT0_M1 & bT0_M0: timer0 mode
|
605 | // 00: mode 0, 13-bit timer or counter by cascaded TH0 and lower 5 bits of TL0, the upper 3 bits of TL0 are ignored
|
606 | // 01: mode 1, 16-bit timer or counter by cascaded TH0 and TL0
|
607 | // 10: mode 2, TL0 operates as 8-bit timer or counter, and TH0 provide initial value for TL0 auto-reload
|
608 | // 11: mode 3, TL0 is 8-bit timer or counter controlled by standard timer0 bits, TH0 is 8-bit timer using TF1 and controlled by TR1, timer1 run enable if it is not mode 3
|
609 |
|
610 | SFR unsigned char TL0 @ 0x8A; // low byte of timer 0 count
|
611 | SFR unsigned char TL1 @ 0x8B; // low byte of timer 1 count
|
612 | SFR unsigned char TH0 @ 0x8C; // high byte of timer 0 count
|
613 | SFR unsigned char TH1 @ 0x8D; // high byte of timer 1 count
|
614 |
|
615 | /* UART0 Registers */
|
616 | SFR union
|
617 | {
|
618 | unsigned char SCON; // UART0 control (serial port control)
|
619 | struct
|
620 | {
|
621 | unsigned char RI : 1; // receive interrupt flag, set by hardware after completion of a serial receiving, need software clear
|
622 | unsigned char TI : 1; // transmit interrupt flag, set by hardware after completion of a serial transmittal, need software clear
|
623 | unsigned char RB8 : 1; // 9th data bit received in mode 2/3, or stop bit received for mode 1
|
624 | unsigned char TB8 : 1; // the 9th transmitted data bit in mode 2/3
|
625 | unsigned char REN : 1; // enable UART0 receiving
|
626 | unsigned char SM2 : 1; // enable multi-device communication in mode 2/3
|
627 | unsigned char SM1 : 1; // UART0 mode bit1, selection baud rate: 0=fixed, 1=variable
|
628 | unsigned char SM0 : 1; // UART0 mode bit0, selection data bit: 0=8 bits data, 1=9 bits data
|
629 | }SCON_bit;
|
630 | }@ 0x98;
|
631 | // SM0 & SM1: UART0 mode
|
632 | // 00 - mode 0, shift Register, baud rate fixed at: Fsys/12
|
633 | // 01 - mode 1, 8-bit UART, baud rate = variable by timer1 or timer2 overflow rate
|
634 | // 10 - mode 2, 9-bit UART, baud rate fixed at: Fsys/128@SMOD=0, Fsys/32@SMOD=1
|
635 | // 11 - mode 3, 9-bit UART, baud rate = variable by timer1 or timer2 overflow rate
|
636 | #define MASK_UART0_MOD 0xE0 // bit mask of UART0 mode
|
637 | #define RI (SCON_bit.RI)
|
638 | #define TI (SCON_bit.TI)
|
639 | #define RB8 (SCON_bit.RB8)
|
640 | #define TB8 (SCON_bit.TB8)
|
641 | #define REN (SCON_bit.REN)
|
642 | #define SM2 (SCON_bit.SM2)
|
643 | #define SM1 (SCON_bit.SM1)
|
644 | #define SM0 (SCON_bit.SM0)
|
645 |
|
646 | SFR unsigned charSBUF @ 0x99; // UART0 data buffer: reading for receiving, writing for transmittal
|
647 |
|
648 | /* Timer2/Capture2 Registers */
|
649 | SFR union
|
650 | {
|
651 | unsigned char T2CON; // timer 2 control
|
652 | struct
|
653 | {
|
654 | unsigned char CP_RL2 : 1; // timer2 function selection (force 0 if RCLK=1 or TCLK=1): 0=timer and auto reload if count overflow or T2EX edge, 1=capture by T2EX edge
|
655 | unsigned char C_T2 : 1; // timer2 clock source selection: 0=timer base internal clock, 1=external edge counter base T2 falling edge
|
656 | unsigned char TR2 : 1; // timer2 run enable
|
657 | unsigned char EXEN2 : 1; // enable T2EX trigger function: 0=ignore T2EX, 1=trigger reload or capture by T2EX edge
|
658 | unsigned char TCLK : 1; // selection UART0 transmittal clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse
|
659 | unsigned char RCLK : 1; // selection UART0 receiving clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse
|
660 | unsigned char EXF2 : 1; // timer2 external flag, set by T2EX edge trigger if EXEN2=1, need software clear
|
661 | unsigned char TF2 : 1; // timer2 overflow & interrupt flag, need software clear, the flag will not be set when either RCLK=1 or TCLK=1
|
662 | }T2Con_bit;
|
663 | }@ 0xC8;
|
664 |
|
665 | #define CP_RL2 (T2CON_bit.CP_RL2)
|
666 | #define C_T2 (T2CON_bit.C_T2)
|
667 | #define TR2 (T2CON_bit.TR2)
|
668 | #define EXEN2 (T2CON_bit.EXEN2)
|
669 | #define TCLK (T2CON_bit.TCLK)
|
670 | #define RCLK (T2CON_bit.RCLK)
|
671 | #define EXF2 (T2CON_bit.EXF2)
|
672 | #define TF2 (T2CON_bit.TF2)
|
673 |
|
674 | SFR unsigned char T2MOD @ 0xC9; // timer 2 mode and timer 0/1/2 clock mode
|
675 | #define bTMR_CLK 0x80 // fastest internal clock mode for timer 0/1/2 under faster clock mode: 0=use divided clock, 1=use original Fsys as clock without dividing
|
676 | #define bT2_CLK 0x40 // timer2 internal clock frequency selection: 0=standard clock, Fsys/12 for timer mode, Fsys/4 for UART0 clock mode,
|
677 | // 1=faster clock, Fsys/4 @bTMR_CLK=0 or Fsys @bTMR_CLK=1 for timer mode, Fsys/2 @bTMR_CLK=0 or Fsys @bTMR_CLK=1 for UART0 clock mode
|
678 | #define bT1_CLK 0x20 // timer1 internal clock frequency selection: 0=standard clock, Fsys/12, 1=faster clock, Fsys/4 if bTMR_CLK=0 or Fsys if bTMR_CLK=1
|
679 | #define bT0_CLK 0x10 // timer0 internal clock frequency selection: 0=standard clock, Fsys/12, 1=faster clock, Fsys/4 if bTMR_CLK=0 or Fsys if bTMR_CLK=1
|
680 | #define bT2_CAP_M1 0x08 // timer2 capture mode high bit
|
681 | #define bT2_CAP_M0 0x04 // timer2 capture mode low bit
|
682 | #define T2OE 0x02 // enable timer2 generated clock output: 0=disable output, 1=enable clock output at T2 pin, frequency = TF2/2
|
683 | #define bT2_CAP1_EN 0x01 // enable T2 trigger function for capture 1 of timer2 if RCLK=0 & TCLK=0 & CP_RL2=1 & C_T2=0 & T2OE=0
|
684 | // bT2_CAP_M1 & bT2_CAP_M0: timer2 capture point selection
|
685 | // x0: from falling edge to falling edge
|
686 | // 01: from any edge to any edge (level changing)
|
687 | // 11: from rising edge to rising edge
|
688 |
|
689 | SFR unsigned int RCAP2 @ 0xCA; // reload & capture value, little-endian
|
690 | SFR unsigned char RCAP2L @ 0xCA; // low byte of reload & capture value
|
691 | SFR unsigned char RCAP2H @ 0xCB; // high byte of reload & capture value
|
692 | SFR unsigned int T2COUNT @ 0xCC; // counter, little-endian
|
693 | SFR unsigned int T2CAP1 @ 0xCC; // ReadOnly: capture 1 value for timer2
|
694 | //#define T2CAP1 T2COUNT
|
695 | SFR unsigned char TL2 @ 0xCC; // low byte of timer 2 count
|
696 | SFR unsigned char T2CAP1L @ 0xCC; // ReadOnly: capture 1 value low byte for timer2
|
697 | //#define T2CAP1L TL2
|
698 | SFR unsigned char TH2 @ 0xCD; // high byte of timer 2 count
|
699 | SFR unsigned char T2CAP1H @ 0xCD; // ReadOnly: capture 1 value high byte for timer2
|
700 | //#define T2CAP1H TH2
|
701 |
|
702 | /* Timer3/Capture3/PWM3 Registers */
|
703 | SFR unsigned char T3_SETUP @ 0xA3; // timer 3 setup
|
704 | #define bT3_IE_END 0x80 // enable interrupt for capture mode count timeout (exceed end value) or PWM mode cycle end
|
705 | #define bT3_IE_FIFO_OV 0x40 // enable interrupt for FIFO overflow
|
706 | #define bT3_IE_FIFO_REQ 0x20 // enable interrupt for capture mode FIFO >=4 or PWM mode FIFO <=3
|
707 | #define bT3_IE_ACT 0x10 // enable interrupt for capture mode input action or PWM mode trigger
|
708 | #define bT3_CAP_IN 0x04 // ReadOnly: current capture input level after noise filtrating
|
709 | #define bT3_CAP_CLK 0x02 // force no minimum pulse width limit for capture input if T3_CK_SE=1
|
710 | #define bT3_EN_CK_SE 0x01 // enable to accessing divisor setting register, else enable to accessing current count register
|
711 |
|
712 | SFR unsigned int T3_COUNT @ 0xA4; // ReadOnly: current count value, little-endian
|
713 | SFR unsigned char T3_COUNT_L @ 0xA4; // ReadOnly: current count low byte
|
714 | SFR unsigned char T3_COUNT_H @ 0xA5; // ReadOnly: current count high byte
|
715 | SFR unsigned int T3_CK_SE @ 0xA4; // clock divisor setting, little-endian, lower 12 bits valid only
|
716 | //#define T3_CK_SE T3_COUNT
|
717 | SFR unsigned char T3_CK_SE_L @ 0xA4; // clock divisor setting low byte
|
718 | //#define T3_CK_SE_L T3_COUNT_L
|
719 | SFR unsigned char T3_CK_SE_H @ 0xA5; // clock divisor setting high byte, lower 4 bits valid only
|
720 | //#define T3_CK_SE_H T3_COUNT_H
|
721 | SFR unsigned int T3_END @ 0xA6; // end value for count, little-endian
|
722 | SFR unsigned char T3_END_L @ 0xA6; // low byte of end value for count
|
723 | SFR unsigned char T3_END_H @ 0xA7; // high byte of end value for count
|
724 | SFR unsigned char T3_STAT @ 0xA9; // timer 3 status
|
725 | #define bT3_IF_DMA_END 0x80 // interrupt flag for DMA completion, write 1 to clear or write T3_DMA_CN to clear
|
726 | #define bT3_IF_FIFO_OV 0x40 // interrupt flag for FIFO overflow, write 1 to clear
|
727 | #define bT3_IF_FIFO_REQ 0x20 // interrupt flag for request FIFO data (capture mode FIFO >=4 or PWM mode FIFO <=3), write 1 to clear
|
728 | #define bT3_IF_ACT 0x10 // interrupt flag for capture mode input action or PWM mode trigger if bT3_IE_ACT=1, write 1 to clear or accessing FIFO to clear
|
729 | #define bT3_IF_END 0x10 // interrupt flag for capture mode count timeout (exceed end value) or PWM mode cycle end if bT3_IE_ACT=0, write 1 to clear
|
730 | #define MASK_T3_FIFO_CNT 0x0F // ReadOnly: bit mask of timer3 FIFO count
|
731 |
|
732 | SFR unsigned char T3_CTRL @ 0xAA; // timer 3 control
|
733 | #define bT3_CAP_M1 0x80 // timer3 capture mode high bit
|
734 | #define bT3_CAP_M0 0x40 // timer3 capture mode low bit
|
735 | #define bT3_PWM_POLAR 0x20 // timer3 PWM output polarity: 0=default low and high action, 1=default high and low action
|
736 | #define bT3_CAP_WIDTH 0x20 // minimum pulse width for timer3 capture: 0=4 divided clocks, 1=1 divided clock
|
737 | #define bT3_DMA_EN 0x10 // DMA enable and DMA interrupt enable for timer3
|
738 | #define bT3_OUT_EN 0x08 // timer3 output enable
|
739 | #define bT3_CNT_EN 0x04 // timer3 count enable
|
740 | #define bT3_CLR_ALL 0x02 // force clear FIFO and count of timer3
|
741 | #define bT3_MOD_CAP 0x01 // timer3 mode: 0=timer or PWM, 1=capture
|
742 | // bT3_CAP_M1 & bT3_CAP_M0: timer3 capture point selection
|
743 | // 00: disable capture
|
744 | // 01: from any edge to any edge (level changing)
|
745 | // 10: from falling edge to falling edge
|
746 | // 11: from rising edge to rising edge
|
747 |
|
748 | SFR unsigned char T3_DMA_CN @ 0xAB; // DMA remainder word count, automatic decreasing after DMA
|
749 | SFR unsigned int T3_DMA @ 0xAC; // DMA address, must even address, little-endian, automatic increasing after DMA
|
750 | SFR unsigned char T3_DMA_AL @ 0xAC; // DMA address low byte, automatic increasing after DMA
|
751 | SFR unsigned char T3_DMA_AH @ 0xAD; // DMA address high byte, automatic increasing after DMA
|
752 | SFR unsigned int T3_FIFO @ 0xAE; // FIFO word, little-endian
|
753 | SFR unsigned char T3_FIFO_L @ 0xAE; // FIFO low byte
|
754 | SFR unsigned char T3_FIFO_H @ 0xAF; // FIFO high byte
|
755 |
|
756 | /* PWM1/2 Registers */
|
757 | SFR unsigned char PWM_DATA2 @ 0x9B; // PWM data for PWM2
|
758 | SFR unsigned char PWM_DATA @ 0x9C; // PWM data for PWM1
|
759 | SFR unsigned char PWM_CTRL @ 0x9D; // PWM 1/2 control
|
760 | #define bPWM_IE_END 0x80 // enable interrupt for PWM mode cycle end or MFM empty buffer
|
761 | #define bPWM2_POLAR 0x40 // PWM2 output polarity if bPWM_MOD_MFM=0: 0=default low and high action, 1=default high and low action
|
762 | #define bMFM_BUF_EMPTY 0x40 // ReadOnly: MFM empty buffer status if bPWM_MOD_MFM=1
|
763 | #define bPWM_POLAR 0x20 // PWM output polarity: 0=default low and high action, 1=default high and low action
|
764 | #define bPWM_IF_END 0x10 // interrupt flag for cycle end, write 1 to clear or write PWM_CYCLE or load new data to clear
|
765 | #define bPWM_OUT_EN 0x08 // PWM1 output enable
|
766 | #define bPWM2_OUT_EN 0x04 // PWM2 output enable if bPWM_MOD_MFM=0
|
767 | #define bMFM_BIT_CNT2 0x04 // ReadOnly: MFM encode bit count status if bPWM_MOD_MFM=1: 0=lower 4 bits, 1=upper 4 bits
|
768 | #define bPWM_CLR_ALL 0x02 // force clear FIFO and count of PWM1/2
|
769 | #define bPWM_MOD_MFM 0x01 // MFM encode mode for PWM: 0=PWM, 1=MFM encode
|
770 | SFR unsigned char PWM_CK_SE @ 0x9E; // clock divisor setting
|
771 | SFR unsigned char PWM_CYCLE @ 0x9F; // PWM cycle
|
772 |
|
773 | /* SPI0/Master0/Slave Registers */
|
774 | SFR union
|
775 | {
|
776 | unsigned char SPI0_STAT; // SPI 0 status
|
777 | struct
|
778 | {
|
779 | unsigned char S0_R_FIFO0 : 1 ; // ReadOnly: rx FIFO count bit0 for SPI0
|
780 | unsigned char S0_R_FIFO1 : 1 ; // ReadOnly: rx FIFO count bit1 for SPI0
|
781 | unsigned char S0_T_FIFO : 1 ; // ReadOnly: tx FIFO count for SPI0
|
782 | unsigned char S0_FREE : 1 ; // ReadOnly: SPI0 free status
|
783 | unsigned char S0_IF_BYTE : 1 ; // interrupt flag for a byte data exchanged, direct bit address clear or write 1 to clear or accessing FIFO to clear if bS0_AUTO_IF=1
|
784 | unsigned char S0_IF_FIRST : 1 ; // interrupt flag for first byte received, direct bit address clear or write 1 to clear
|
785 | unsigned char S0_IF_OV : 1 ; // interrupt flag for slave mode FIFO overflow, direct bit address clear or write 1 to clear
|
786 | unsigned char S0_FST_ACT : 1 ; // ReadOnly: indicate first byte received status for SPI0
|
787 | }SPI0_STAT_bit;
|
788 | }@ 0xF8;
|
789 | #define MASK_S0_RFIFO_CNT 0x03 // ReadOnly: bit mask of SPI0 rx FIFO count
|
790 |
|
791 | #define S0_R_FIFO0 (SPI0_STAT_bit.S0_R_FIFO0)
|
792 | #define S0_R_FIFO1 (SPI0_STAT_bit.S0_R_FIFO1)
|
793 | #define S0_T_FIFO (SPI0_STAT_bit.S0_T_FIFO)
|
794 | #define S0_FREE (SPI0_STAT_bit.S0_FREE)
|
795 | #define S0_IF_BYTE (SPI0_STAT_bit.S0_IF_BYTE)
|
796 | #define S0_IF_FIRST (SPI0_STAT_bit.S0_IF_FIRST)
|
797 | #define S0_IF_OV (SPI0_STAT_bit.S0_IF_OV)
|
798 | #define S0_FST_ACT (SPI0_STAT_bit.S0_FST_ACT)
|
799 |
|
800 | SFR unsigned char SPI0_DATA @ 0xF9; // FIFO data port: reading for receiving, writing for transmittal
|
801 | SFR unsigned char SPI0_CTRL @ 0xFA; // SPI 0 control
|
802 | #define bS0_MISO_OE 0x80 // SPI0 MISO output enable
|
803 | #define bS0_MOSI_OE 0x40 // SPI0 MOSI output enable
|
804 | #define bS0_SCK_OE 0x20 // SPI0 SCK output enable
|
805 | #define bS0_DATA_DIR 0x10 // SPI0 data direction: 0=out(master_write), 1=in(master_read)
|
806 | #define bS0_MST_CLK 0x08 // SPI0 master clock mode: 0=mode 0 with default low, 1=mode 3 with default high
|
807 | #define bS0_2_WIRE 0x04 // enable SPI0 two wire mode: 0=3 wire (SCK+MOSI+MISO), 1=2 wire (SCK+MISO)
|
808 | #define bS0_CLR_ALL 0x02 // force clear FIFO and count of SPI0
|
809 | #define bS0_AUTO_IF 0x01 // enable FIFO accessing to auto clear S0_IF_BYTE interrupt flag
|
810 |
|
811 | SFR unsigned char SPI0_CK_SE @ 0xFB; // clock divisor setting
|
812 | SFR unsigned char SPI0_S_PRE @ 0xFB; // preset value for SPI slave
|
813 | // #define SPI0_S_PRE SPI0_CK_SE
|
814 | SFR unsigned char SPI0_SETUP @ 0xFC; // SPI 0 setup
|
815 | #define bS0_MODE_SLV 0x80 // SPI0 slave mode: 0=master, 1=slave
|
816 | #define bS0_IE_FIFO_OV 0x40 // enable interrupt for slave mode FIFO overflow
|
817 | #define bS0_IE_FIRST 0x20 // enable interrupt for first byte received for SPI0 slave mode
|
818 | #define bS0_IE_BYTE 0x10 // enable interrupt for a byte received
|
819 | #define bS0_BIT_ORDER 0x08 // SPI0 bit data order: 0=MSB first, 1=LSB first
|
820 | #define bS0_SLV_SELT 0x02 // ReadOnly: SPI0 slave mode chip selected status: 0=unselected, 1=selected
|
821 | #define bS0_SLV_PRELOAD 0x01 // ReadOnly: SPI0 slave mode data pre-loading status just after chip-selection
|
822 |
|
823 | /* SPI1/Master1 Registers */
|
824 | SFR unsigned char SPI1_STAT @ 0xB4; // SPI 1 status
|
825 | #define bS1_IF_BYTE 0x10 // interrupt flag for a byte data exchanged, write 1 to clear or accessing FIFO to clear if bS1_AUTO_IF=1
|
826 | #define bS1_FREE 0x08 // ReadOnly: SPI1 free status
|
827 |
|
828 | SFR unsigned char SPI1_DATA @ 0xB5; // data port: reading for receiving, writing for transmittal
|
829 | SFR unsigned char SPI1_CTRL @ 0xB6; // SPI 1 control
|
830 | #define bS1_MISO_OE 0x80 // SPI1 MISO output enable
|
831 | #define bS1_SCK_OE 0x20 // SPI1 SCK output enable, MOSI output enable if bS1_2_WIRE=0
|
832 | #define bS1_DATA_DIR 0x10 // SPI1 data direction: 0=out(master_write), 1=in(master_read)
|
833 | #define bS1_MST_CLK 0x08 // SPI1 master clock mode: 0=mode 0 with default low, 1=mode 3 with default high
|
834 | #define bS1_2_WIRE 0x04 // enable SPI1 two wire mode: 0=3 wire (SCK+MOSI+MISO), 1=2 wire (SCK+MISO)
|
835 | #define bS1_CLR_ALL 0x02 // force clear FIFO and count of SPI1
|
836 | #define bS1_AUTO_IF 0x01 // enable FIFO accessing to auto clear bS1_IF_BYTE interrupt flag
|
837 |
|
838 | SFR unsigned char SPI1_CK_SE @ 0xB7; // clock divisor setting
|
839 |
|
840 | /* UART1/iRS485 Registers */
|
841 | SFR unsigned char SER1_FIFO @ 0x9A; // UART1 FIFO data port: reading for receiving, writing for transmittal
|
842 | SFR unsigned char SER1_RBR @ 0x9A; // ReadOnly: UART1 receiver buffer
|
843 | //#define SER1_RBR SER1_FIFO
|
844 | SFR unsigned char SER1_THR @ 0x9A; // WriteOnly: UART1 transmitter holding
|
845 | //#define SER1_THR SER1_FIFO
|
846 | SFR unsigned char SER1_IER @ 0x91; // UART1 interrupt enable
|
847 | #define bIER_RESET 0x80 // UART1 software reset control, high action, auto clear
|
848 | #define bIER_EN_MODEM_O 0x40 // enable UART1 modem output signal, DTR connect P0.0, RTS connect P0.1
|
849 | #define bIER_PIN_MOD1 0x20 // UART1 pin mode high bit
|
850 | #define bIER_PIN_MOD0 0x10 // UART1 pin mode low bit
|
851 | #define MASK_U1_PIN_MOD 0x70 // bit mask of UART1 pin mode
|
852 | // RS485EN & bIER_PIN_MOD1 & bIER_PIN_MOD0: UART1 pin mode
|
853 | // RS485EN = bUH1_DISABLE & ~ ( bXBUS_CS_OE & ~ bXBUS_AL_OE | bALE_CLK_EN )
|
854 | // x00: RXD1 connect P4.0, disable TXD1
|
855 | // 010: RXD1/TXD1 connect P2.6/P2.7
|
856 | // 001: RXD1/TXD1 connect P4.0/P4.4
|
857 | // 011: RXD1/TXD1/TNOW connect P2.6/P2.7/P2.5
|
858 | // 110: RXD1/TXD1 connect iRS485 pins XA/XB
|
859 | // 101: RXD1/TXD1 connect iRS485 pins XA/XB, TNOW connect P4.4
|
860 | // 111: RXD1/TXD1 connect iRS485 pins XA/XB, TNOW connect P2.5
|
861 | #define bIER_MODEM_CHG 0x08 // UART1 interrupt enable for modem status change
|
862 | #define bIER_LINE_STAT 0x04 // UART1 interrupt enable for receiver line status
|
863 | #define bIER_THR_EMPTY 0x02 // UART1 interrupt enable for THR empty
|
864 | #define bIER_RECV_RDY 0x01 // UART1 interrupt enable for receiver data ready
|
865 |
|
866 | SFR unsigned char SER1_IIR @ 0x92; // ReadOnly: UART1 interrupt identification
|
867 | #define MASK_U1_IIR_ID 0xC0 // ReadOnly: bit mask of UART1 IIR, FIFO enabled flag
|
868 | #define bIIR_INT_FLAG3 0x08 // ReadOnly: UART1 interrupt flag bit 3
|
869 | #define bIIR_INT_FLAG2 0x04 // ReadOnly: UART1 interrupt flag bit 2
|
870 | #define bIIR_INT_FLAG1 0x02 // ReadOnly: UART1 interrupt flag bit 1
|
871 | #define bIIR_INT_FLAG0 0x01 // ReadOnly: UART1 interrupt flag bit 0
|
872 | #define MASK_U1_IIR_INT 0x0F // ReadOnly: bit mask of UART1 interrupt flag
|
873 | // bIIR_INT_FLAG3 & bIIR_INT_FLAG2 & bIIR_INT_FLAG1 & bIIR_INT_FLAG0: UART1 interrupt flag, list follow:
|
874 | #define U1_INT_SLV_ADDR 0x0E // UART1 interrupt by slave address match
|
875 | #define U1_INT_LINE_STAT 0x06 // UART1 interrupt by receiver line status
|
876 | #define U1_INT_RECV_RDY 0x04 // UART1 interrupt by receiver data available
|
877 | #define U1_INT_RECV_TOUT 0x0C // UART1 interrupt by receiver FIFO timeout
|
878 | #define U1_INT_THR_EMPTY 0x02 // UART1 interrupt by THR empty
|
879 | #define U1_INT_MODEM_CHG 0x00 // UART1 interrupt by modem status change
|
880 | #define U1_INT_NO_INTER 0x01 // no UART interrupt is pending
|
881 | #define bIIR_NO_INT 0x01 // UART1 no interrupt flag: 0=interrupt action, 1=no interrupt
|
882 |
|
883 | SFR unsigned char SER1_FCR @ 0x92; // WriteOnly: UART1 FIFO control
|
884 | //#define SER1_FCR SER1_IIR
|
885 | #define bFCR_FIFO_TRIG1 0x80 // UART1 receiver FIFO trigger level high bit
|
886 | #define bFCR_FIFO_TRIG0 0x40 // UART1 receiver FIFO trigger level low bit
|
887 | #define MASK_U1_FIFO_TRIG 0xC0 // bit mask of UART1 receiver FIFO trigger level
|
888 | // bFCR_FIFO_TRIG1 & bFCR_FIFO_TRIG0: UART1 receiver FIFO trigger level
|
889 | // 00: 1 byte
|
890 | // 01: 2 bytes
|
891 | // 10: 4 bytes
|
892 | // 11: 7 bytes
|
893 | #define bFCR_T_FIFO_CLR 0x04 // clear UART1 transmitter FIFO, high action, auto clear
|
894 | #define bFCR_R_FIFO_CLR 0x02 // clear UART1 receiver FIFO, high action, auto clear
|
895 | #define bFCR_FIFO_EN 0x01 // UART1 FIFO enable
|
896 |
|
897 | SFR unsigned char SER1_LCR @ 0x93; // UART1 line control
|
898 | #define bLCR_DLAB 0x80 // UART1 divisor latch access bit
|
899 | #define bLCR_BREAK_EN 0x40 // UART1 break control enable
|
900 | #define bLCR_PAR_MOD1 0x20 // UART1 parity mode high bit
|
901 | #define bLCR_PAR_MOD0 0x10 // UART1 parity mode low bit
|
902 | #define MASK_U1_PAR_MOD 0x30 // bit mask of UART1 parity mode
|
903 | #define U1_PAR_MOD_ODD 0x00
|
904 | #define U1_PAR_MOD_EVEN 0x10
|
905 | #define U1_PAR_MOD_MARK 0x20
|
906 | #define U1_PAR_MOD_SPACE 0x30
|
907 | // bLCR_PAR_MOD1 & bLCR_PAR_MOD0: UART1 parity mode if bLCR_PAR_EN=1, else ignored
|
908 | // 00: the 9th bit is odd parity bit
|
909 | // 01: the 9th bit is even parity bit
|
910 | // 10: the 9th bit is mark bit
|
911 | // 11: the 9th bit is space bit
|
912 | #define bLCR_PAR_EN 0x08 // UART1 parity enable
|
913 | #define bLCR_STOP_BIT 0x04 // UART1 stop bit length: 0=1 bit, 1=2 bits
|
914 | #define bLCR_WORD_SZ1 0x02 // UART1 word bit length high
|
915 | #define bLCR_WORD_SZ0 0x01 // UART1 word bit length low
|
916 | #define MASK_U1_WORD_SZ 0x03 // bit mask of UART1 word bit length
|
917 | // bLCR_WORD_SZ1 & bLCR_WORD_SZ0: UART1 word bit length (exclude parity bit)
|
918 | // 00: 5 bits
|
919 | // 01: 6 bits
|
920 | // 10: 7 bits
|
921 | // 11: 8 bits
|
922 |
|
923 | SFR unsigned char SER1_MCR @ 0x94; // UART1 modem control
|
924 | #define bMCR_HALF 0x80 // UART1 enable half-duplex mode
|
925 | #define bMCR_TNOW 0x40 // UART1 enable TNOW output on DTR pin
|
926 | #define bMCR_AUTO_FLOW 0x20 // UART1 enable autoflow control by CTS & RTS pin
|
927 | #define bMCR_LOOP 0x10 // UART1 enable local loop back for testing
|
928 | #define bMCR_OUT2 0x08 // UART1 control OUT2, enable interrupt request output
|
929 | #define bMCR_OUT1 0x04 // UART1 control OUT1, not real pin
|
930 | #define bMCR_RTS 0x02 // UART1 control RTS
|
931 | #define bMCR_DTR 0x01 // UART1 control DTR
|
932 |
|
933 | SFR unsigned char SER1_LSR @ 0x95; // ReadOnly: UART1 line status
|
934 | #define bLSR_ERR_R_FIFO 0x80 // ReadOnly: error in UART1 receiver fifo, read to clear
|
935 | #define bLSR_T_ALL_EMP 0x40 // ReadOnly: UART1 transmitter all empty status
|
936 | #define bLSR_T_FIFO_EMP 0x20 // ReadOnly: UART1 transmitter FIFO empty status
|
937 | #define bLSR_BREAK_ERR 0x10 // ReadOnly: UART1 receiver break error, read to clear
|
938 | #define bLSR_FRAME_ERR 0x08 // ReadOnly: UART1 receiver frame error, read to clear
|
939 | #define bLSR_PAR_ERR 0x04 // ReadOnly: UART1 receiver parity error, read to clear
|
940 | #define bLSR_OVER_ERR 0x02 // ReadOnly: UART1 receiver overrun error, read to clear
|
941 | #define bLSR_DATA_RDY 0x01 // ReadOnly: UART1 receiver FIFO data ready status
|
942 |
|
943 | SFR unsigned char SER1_MSR @ 0x96; // ReadOnly: UART1 modem status
|
944 | #define bMSR_DCD 0x80 // ReadOnly: UART1 DCD action status
|
945 | #define bMSR_RI 0x40 // ReadOnly: UART1 RI action status
|
946 | #define bMSR_DSR 0x20 // ReadOnly: UART1 DSR action status
|
947 | #define bMSR_CTS 0x10 // ReadOnly: UART1 CTS action status
|
948 | #define bMSR_DCD_CHG 0x08 // ReadOnly: UART1 DCD changed status, high action, read to clear
|
949 | #define bMSR_RI_CHG 0x04 // ReadOnly: UART1 RI changed status, high action, read to clear
|
950 | #define bMSR_DSR_CHG 0x02 // ReadOnly: UART1 DSR changed status, high action, read to clear
|
951 | #define bMSR_CTS_CHG 0x01 // ReadOnly: UART1 CTS changed status, high action, read to clear
|
952 |
|
953 | SFR unsigned char SER1_ADDR @ 0x97; // UART1 slave address for multi-device communication, value 0xFF is disable
|
954 | SFR unsigned char SER1_DLL @ 0x9A; // UART1 divisor latch LSB byte if bLCR_DLAB=1
|
955 | //#define SER1_DLL SER1_FIFO
|
956 | SFR unsigned char SER1_DLM @ 0x91; // UART1 divisor latch MSB byte if bLCR_DLAB=1
|
957 | //#define SER1_DLM SER1_IER
|
958 | SFR unsigned char SER1_DIV @ 0x97; // UART1 pre-divisor latch byte if bLCR_DLAB=1
|
959 | //#define SER1_DIV SER1_ADDR
|
960 |
|
961 | /* ADC Registers */
|
962 | SFR unsigned int ADC_DMA @ 0xEC; // DMA address, must even address, little-endian, automatic increasing after DMA
|
963 | SFR unsigned char ADC_DMA_AL @ 0xEC; // DMA address low byte, automatic increasing after DMA
|
964 | SFR unsigned char ADC_DMA_AH @ 0xED; // DMA address high byte, automatic increasing after DMA
|
965 | SFR unsigned char ADC_DMA_CN @ 0xEE; // DMA remainder word count, automatic decreasing after DMA
|
966 | SFR unsigned char ADC_CK_SE @ 0xEF; // ADC clock divisor setting
|
967 | #define MASK_ADC_CK_SE 0x7F // bit mask of ADC clock divisor
|
968 | #define bADC_CHK_CLK_SEL 0x80 // AIN7 level check delay clock frequency selection: 0=slow(1x), 1=fast(4x)
|
969 |
|
970 | SFR unsigned char ADC_STAT @ 0xF1; // ADC status
|
971 | #define bADC_IF_DMA_END 0x80 // interrupt flag for DMA completion, write 1 to clear or write ADC_DMA_CN to clear
|
972 | #define bADC_IF_FIFO_OV 0x40 // interrupt flag for FIFO overflow, write 1 to clear
|
973 | #define bADC_IF_AIN7_LOW 0x20 // interrupt flag for AIN7 low level, write 1 to clear
|
974 | #define bADC_IF_ACT 0x10 // interrupt flag for a ADC finished, write 1 to clear
|
975 | #define bADC_AIN7_INT 0x08 // ReadOnly: current AIN7 low level delay status
|
976 | #define bADC_CHANN_ID 0x04 // ReadOnly: current channel ID for channel automatic switch mode: 0=AIN0 or AIN6, 1=AIN1 or AIN4 or AIN7
|
977 | #define bADC_DATA_OK 0x04 // ReadOnly: ADC end and data ready flag for channel manual selection mode: 0=data not ready, 1=data ready
|
978 | #define bADC_FIFO_CNT1 0x02 // ReadOnly: ADC FIFO count bit 1
|
979 | #define bADC_FIFO_CNT0 0x01 // ReadOnly: ADC FIFO count bit 0
|
980 | #define MASK_ADC_FIFO_CNT 0x03 // ReadOnly: bit mask of ADC FIFO count
|
981 | // bADC_FIFO_CNT1 & bADC_FIFO_CNT0: ADC FIFO count
|
982 | // 00: empty FIFO, return current ADC result if reading FIFO
|
983 | // 01: 1 result in FIFO
|
984 | // 01: 2 results in FIFO, FIFO full
|
985 | // 11: unknown error
|
986 |
|
987 | SFR unsigned char ADC_CTRL @ 0xF2; // ADC control
|
988 | #define bADC_SAMPLE 0x80 // automatic or manual sample pulse control, high action
|
989 | #define bADC_SAMP_WIDTH 0x40 // automatic sample pulse width: 0=1 ADC clock, 1=2 ADC clocks
|
990 | #define bADC_CHANN_MOD1 0x20 // ADC channel control mode high bit
|
991 | #define bADC_CHANN_MOD0 0x10 // ADC channel control mode low bit
|
992 | #define MASK_ADC_CHANN 0x30 // bit mask of ADC channel control mode
|
993 | // bADC_CHANN_MOD1 & bADC_CHANN_MOD0: ADC channel control mode
|
994 | // 00: manual selection by ADC_CHANN bit
|
995 | // 01: automatic switch between AIN0 and AIN1
|
996 | // 10: automatic switch between AIN6 and AIN4
|
997 | // 11: automatic switch between AIN6 and AIN7
|
998 | #define MASK_ADC_CYCLE 0x0F // bit mask of ADC cycle (ADC clock number): 0=manual sample, others=set cycle number for automatic sample
|
999 |
|
1000 | SFR unsigned char ADC_CHANN @ 0xF3; // ADC channel seletion
|
1001 | SFR unsigned int ADC_FIFO @ 0xF4; // ReadOnly: FIFO word, little-endian
|
1002 | SFR unsigned char ADC_FIFO_L @ 0xF4; // ReadOnly: FIFO low byte
|
1003 | SFR unsigned char ADC_FIFO_H @ 0xF5; // ReadOnly: FIFO high byte
|
1004 | SFR unsigned char ADC_SETUP @ 0xF6; // ADC setup
|
1005 | #define bADC_DMA_EN 0x80 // DMA enable and DMA interrupt enable for ADC
|
1006 | #define bADC_IE_FIFO_OV 0x40 // enable interrupt for FIFO overflow
|
1007 | #define bADC_IE_AIN7_LOW 0x20 // enable interrupt for AIN7 low level
|
1008 | #define bADC_IE_ACT 0x10 // enable interrupt for a ADC finished
|
1009 | #define bADC_CLOCK 0x08 // ReadOnly: current level of ADC clock
|
1010 | #define bADC_POWER_EN 0x04 // control ADC power: 0=shut down ADC, 1=enable power for ADC
|
1011 | #define bADC_EXT_SW_EN 0x02 // control extend switch module power: 0=shut down, 1=enable power for extend switch
|
1012 | #define bADC_AIN7_CHK_EN 0x01 // control AIN7 level check module power: 0=shut down, 1=enable power for AIN7 level check
|
1013 |
|
1014 | SFR unsigned char ADC_EX_SW @ 0xF7; // ADC extend switch control
|
1015 | #define bADC_SW_AIN7_H 0x80 // internal AIN7 extend switch control: 0=float AIN7, 1=tie AIN7 to high level VDD33
|
1016 | #define bADC_SW_AIN6_L 0x40 // internal AIN6 extend switch control: 0=float AIN6, 1=tie AIN6 to low level GND
|
1017 | #define bADC_SW_AIN5_H 0x20 // internal AIN5 extend switch control: 0=float AIN5, 1=tie AIN5 to high level VDD33
|
1018 | #define bADC_SW_AIN4_L 0x10 // internal AIN4 extend switch control: 0=float AIN4, 1=tie AIN4 to low level GND
|
1019 | #define bADC_EXT_SW_SEL 0x08 // extend switch resistance selection: 0=high resistance, 1=low resistance
|
1020 | #define bADC_RESOLUTION 0x04 // ADC resolution: 0=10 bits, 1=11 bits
|
1021 | #define bADC_AIN7_DLY1 0x02 // AIN7 level check delay control bit 1
|
1022 | #define bADC_AIN7_DLY0 0x01 // AIN7 level check delay control bit 0
|
1023 | #define MASK_ADC_AIN7_DLY 0x03 // bit mask for AIN7 check delay control: 01=longest, 10=longer, 11=shorter, 00=shortest (no delay)
|
1024 |
|
1025 | /* USB/Host/Device Registers */
|
1026 | SFR unsigned char USB_RX_LEN @ 0xD1; // ReadOnly: USB receiving length
|
1027 |
|
1028 | SFR unsigned char UEP1_CTRL @ 0xD2; // endpoint 1 control
|
1029 | #define bUEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
|
1030 | #define bUEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
|
1031 | #define bUEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
|
1032 | #define bUEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT)
|
1033 | #define bUEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT)
|
1034 | #define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT)
|
1035 | #define UEP_R_RES_ACK 0x00
|
1036 | #define UEP_R_RES_TOUT 0x04
|
1037 | #define UEP_R_RES_NAK 0x08
|
1038 | #define UEP_R_RES_STALL 0x0C
|
1039 | // bUEP_R_RES1 & bUEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
|
1040 | // 00: ACK (ready)
|
1041 | // 01: no response, time out to host, for non-zero endpoint isochronous transactions
|
1042 | // 10: NAK (busy)
|
1043 | // 11: STALL (error)
|
1044 | #define bUEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN)
|
1045 | #define bUEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN)
|
1046 | #define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN)
|
1047 | #define UEP_T_RES_ACK 0x00
|
1048 | #define UEP_T_RES_TOUT 0x01
|
1049 | #define UEP_T_RES_NAK 0x02
|
1050 | #define UEP_T_RES_STALL 0x03
|
1051 | // bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
|
1052 | // 00: DATA0 or DATA1 then expecting ACK (ready)
|
1053 | // 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
|
1054 | // 10: NAK (busy)
|
1055 | // 11: STALL (error)
|
1056 | SFR unsigned char UEP1_T_LEN @ 0xD3; // endpoint 1 transmittal length
|
1057 | SFR unsigned char UEP2_CTRL @ 0xD4; // endpoint 2 control
|
1058 | SFR unsigned char UEP2_T_LEN @ 0xD5; // endpoint 2 transmittal length
|
1059 | SFR unsigned char UEP3_CTRL @ 0xD6; // endpoint 3 control
|
1060 | SFR unsigned char UEP3_T_LEN @ 0xD7; // endpoint 3 transmittal length
|
1061 |
|
1062 | SFR union
|
1063 | {
|
1064 | unsigned char USB_INT_FG; // USB interrupt flag
|
1065 | struct
|
1066 | {
|
1067 | unsigned char UIF_BUS_RST : 1; // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
|
1068 | unsigned char UIF_TRANSFER : 1; // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
|
1069 | unsigned char UIF_SUSPEND : 1; // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
|
1070 | unsigned char UIF_HST_SOF : 1; // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
|
1071 | unsigned char UIF_FIFO_OV : 1; // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
|
1072 | unsigned char U_SIE_FREE : 1; // ReadOnly: indicate USB SIE free status
|
1073 | unsigned char U_TOG_OK : 1; // ReadOnly: indicate current USB transfer toggle is OK
|
1074 | unsigned char U_IS_NAK : 1; // ReadOnly: indicate current USB transfer is NAK received
|
1075 | }USB_INT_FG_bit;
|
1076 | }@ 0xD8;
|
1077 | #define UIF_BUS_RST (USB_INT_FG_bit.UIF_BUS_RST)
|
1078 | #define UIF_DETECT (USB_INT_FG_bit.UIF_BUS_RST) // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
|
1079 | #define UIF_TRANSFER (USB_INT_FG_bit.UIF_TRANSFER)
|
1080 | #define UIF_SUSPEND (USB_INT_FG_bit.UIF_SUSPEND)
|
1081 | #define UIF_HST_SOF (USB_INT_FG_bit.UIF_HST_SOF)
|
1082 | #define UIF_FIFO_OV (USB_INT_FG_bit.UIF_FIFO_OV)
|
1083 | #define U_SIE_FREE (USB_INT_FG_bit.U_SIE_FREE)
|
1084 | #define U_TOG_OK (USB_INT_FG_bit.U_TOG_OK)
|
1085 | #define U_IS_NAK (USB_INT__FGbit.U_IS_NAK)
|
1086 |
|
1087 |
|
1088 | SFR unsigned char USB_INT_ST @ 0xD9; // ReadOnly: USB interrupt status
|
1089 | #define bUIS_IS_NAK 0x80 // ReadOnly: indicate current USB transfer is NAK received for USB device mode
|
1090 | #define bUIS_TOG_OK 0x40 // ReadOnly: indicate current USB transfer toggle is OK
|
1091 | #define bUIS_TOKEN1 0x20 // ReadOnly: current token PID code bit 1 received for USB device mode
|
1092 | #define bUIS_TOKEN0 0x10 // ReadOnly: current token PID code bit 0 received for USB device mode
|
1093 | #define MASK_UIS_TOKEN 0x30 // ReadOnly: bit mask of current token PID code received for USB device mode
|
1094 | #define UIS_TOKEN_OUT 0x00
|
1095 | #define UIS_TOKEN_SOF 0x10
|
1096 | #define UIS_TOKEN_IN 0x20
|
1097 | #define UIS_TOKEN_SETUP 0x30
|
1098 | // bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
|
1099 | // 00: OUT token PID received
|
1100 | // 01: SOF token PID received
|
1101 | // 10: IN token PID received
|
1102 | // 11: SETUP token PID received
|
1103 | #define MASK_UIS_ENDP 0x0F // ReadOnly: bit mask of current transfer endpoint number for USB device mode
|
1104 | #define MASK_UIS_H_RES 0x0F // ReadOnly: bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
|
1105 |
|
1106 | SFR unsigned char USB_MIS_ST @ 0xDA; // ReadOnly: USB miscellaneous status
|
1107 | #define bUMS_SOF_PRES 0x80 // ReadOnly: indicate host SOF timer presage status
|
1108 | #define bUMS_SOF_ACT 0x40 // ReadOnly: indicate host SOF timer action status for USB host
|
1109 | #define bUMS_SIE_FREE 0x20 // ReadOnly: indicate USB SIE free status
|
1110 | #define bUMS_R_FIFO_RDY 0x10 // ReadOnly: indicate USB receiving FIFO ready status (not empty)
|
1111 | #define bUMS_BUS_RESET 0x08 // ReadOnly: indicate USB bus reset status
|
1112 | #define bUMS_SUSPEND 0x04 // ReadOnly: indicate USB suspend status
|
1113 | #define bUMS_H1_ATTACH 0x02 // ReadOnly: indicate device attached status on USB hub1 HP/HM
|
1114 | #define bUMS_H0_ATTACH 0x01 // ReadOnly: indicate device attached status on USB hub0 DP/DM
|
1115 |
|
1116 | SFR unsigned char USB_HUB_ST @ 0xDB; // ReadOnly: USB host hub status
|
1117 | #define bUHS_H1_ATTACH 0x80 // ReadOnly: indicate device attached status on USB hub1 HP/HM
|
1118 | #define bUHS_HM_LEVEL 0x40 // ReadOnly: indicate HM level saved at device attached to USB hub1
|
1119 | #define bUHS_HP_PIN 0x20 // ReadOnly: indicate current HP pin level
|
1120 | #define bUHS_HM_PIN 0x10 // ReadOnly: indicate current HM pin level
|
1121 | #define bUHS_H0_ATTACH 0x08 // ReadOnly: indicate device attached status on USB hub0 DP/DM
|
1122 | #define bUHS_DM_LEVEL 0x04 // ReadOnly: indicate DM level saved at device attached to USB hub0
|
1123 | #define bUHS_DP_PIN 0x02 // ReadOnly: indicate current DP pin level
|
1124 | #define bUHS_DM_PIN 0x01 // ReadOnly: indicate current DM pin level
|
1125 |
|
1126 | SFR unsigned char UEP0_CTRL @ 0xDC; // endpoint 0 control
|
1127 | SFR unsigned char UEP0_T_LEN @ 0xDD; // endpoint 0 transmittal length
|
1128 | SFR unsigned char UEP4_CTRL @ 0xDE; // endpoint 4 control
|
1129 | SFR unsigned char UEP4_T_LEN @ 0xDF; // endpoint 4 transmittal length
|
1130 | SFR unsigned char USB_INT_EN @ 0xE1; // USB interrupt enable
|
1131 | #define bUIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode
|
1132 | #define bUIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode
|
1133 | #define bUIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow
|
1134 | #define bUIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode
|
1135 | #define bUIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event
|
1136 | #define bUIE_TRANSFER 0x02 // enable interrupt for USB transfer completion
|
1137 | #define bUIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode
|
1138 | #define bUIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode
|
1139 |
|
1140 | SFR unsigned char USB_CTRL @ 0xE2; // USB base control
|
1141 | #define bUC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode
|
1142 | #define bUC_LOW_SPEED 0x40 // enable USB low speed: 0=full speed, 1=low speed
|
1143 | #define bUC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable
|
1144 | #define bUC_SYS_CTRL1 0x20 // USB system control high bit
|
1145 | #define bUC_SYS_CTRL0 0x10 // USB system control low bit
|
1146 | #define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control
|
1147 | // bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control
|
1148 | // 0 00: disable USB device and disable internal pullup resistance
|
1149 | // 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance
|
1150 | // 0 10: enable USB device and enable internal pullup resistance
|
1151 | // 0 11: enable USB device and enable internal weak pullup resistance
|
1152 | // 1 00: enable USB host and normal status
|
1153 | // 1 01: enable USB host and force DP/DM output SE0 state
|
1154 | // 1 10: enable USB host and force DP/DM output J state
|
1155 | // 1 11: enable USB host and force DP/DM output resume or K state
|
1156 | #define bUC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid
|
1157 | #define bUC_RESET_SIE 0x04 // force reset USB SIE, need software clear
|
1158 | #define bUC_CLR_ALL 0x02 // force clear FIFO and count of USB
|
1159 | #define bUC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB
|
1160 |
|
1161 | SFR unsigned char USB_DEV_AD @ 0xE3; // USB device address, lower 7 bits for USB device address
|
1162 | #define bUDA_GP_BIT 0x80 // general purpose bit
|
1163 | #define MASK_USB_ADDR 0x7F // bit mask for USB device address
|
1164 |
|
1165 | SFR unsigned char UDEV_CTRL @ 0xE4; // USB device physical port control
|
1166 | #define bUD_RECV_DIS 0x40 // disable USB physical port receiver: 0=enable receiver, 1=disable receiver
|
1167 | #define bUD_DP_PD_DIS 0x20 // disable USB DP pulldown resistance: 0=enable pulldown, 1=disable
|
1168 | #define bUD_DM_PD_DIS 0x10 // disable USB DM pulldown resistance: 0=enable pulldown, 1=disable
|
1169 | #define bUD_DIFF_IN 0x08 // ReadOnly: indicate current DP/DM difference input status
|
1170 | #define bUD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
|
1171 | #define bUD_GP_BIT 0x02 // general purpose bit
|
1172 | #define bUD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable
|
1173 |
|
1174 | SFR unsigned char UHUB0_CTRL @ 0xE4; // USB hub0 control
|
1175 | // #define UHUB0_CTRL UDEV_CTRL
|
1176 | #define bUH_RECV_DIS 0x40 // disable USB hub receiver: 0=enable hub receiver, 1=disable hub receiver
|
1177 | #define bUH_DP_PD_DIS 0x20 // disable USB DP or HP pulldown resistance: 0=enable pulldown, 1=disable
|
1178 | #define bUH_DM_PD_DIS 0x10 // disable USB DM or HM pulldown resistance: 0=enable pulldown, 1=disable
|
1179 | #define bUH_DIFF_IN 0x08 // ReadOnly: indicate current DP/DM or HP/HM difference input status
|
1180 | #define bUH_LOW_SPEED 0x04 // enable USB hub low speed: 0=full speed, 1=low speed
|
1181 | #define bUH_BUS_RESET 0x02 // control USB hub bus reset: 0=normal, 1=force bus reset
|
1182 | #define bUH_PORT_EN 0x01 // enable USB hub port: 0=disable, 1=enable port, automatic disabled if USB device detached
|
1183 |
|
1184 | SFR unsigned char UHUB1_CTRL @ 0xE5; // USB hub1 control
|
1185 | #define bUH1_DISABLE 0x80 // disable USB hub1 pin: 0=enable hub1 and using HP/HM pin, 1=disable hub1 and releasing HP/HM pin
|
1186 | SFR unsigned int USB_DMA @ 0xE6; // ReadOnly: current DMA address, little-endian
|
1187 | SFR unsigned char USB_DMA_AL @ 0xE6; // ReadOnly: current DMA address low byte
|
1188 | SFR unsigned char USB_DMA_AH @ 0xE7; // ReadOnly: current DMA address high byte
|
1189 | SFR unsigned char UH_SETUP @ 0xD2; // host aux setup
|
1190 | // #define UH_SETUP UEP1_CTRL
|
1191 | #define bUH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub
|
1192 | #define bUH_SOF_EN 0x40 // USB host automatic SOF enable
|
1193 | SFR unsigned char UH_RX_CTRL @ 0xD4; // host receiver endpoint control
|
1194 | // #define UH_RX_CTRL UEP2_CTRL
|
1195 | #define bUH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
|
1196 | #define bUH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
1197 | #define bUH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
|
1198 |
|
1199 | SFR unsigned char UH_EP_PID @ 0xD5; // host endpoint and token PID, lower 4 bits for endpoint number, upper 4 bits for token PID
|
1200 | //#define UH_EP_PID UEP2_T_LEN
|
1201 | #define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer
|
1202 | #define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer
|
1203 |
|
1204 | SFR unsigned char UH_TX_CTRL @ 0xD6; // host transmittal endpoint control
|
1205 | //#define UH_TX_CTRL UEP3_CTRL
|
1206 | #define bUH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
|
1207 | #define bUH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
1208 | #define bUH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
|
1209 |
|
1210 | SFR unsigned char UH_TX_LEN @ 0xD7; // host transmittal endpoint transmittal length
|
1211 | //#define UH_TX_LEN UEP3_T_LEN
|
1212 |
|
1213 | /*----- XDATA: xRAM, xBUS, xSFR ------------------------------------------*/
|
1214 |
|
1215 | #define XDATA_RAM_SIZE 0x1800 // size of expanded xRAM, xdata SRAM embedded chip
|
1216 | #define XDATA_XBUS_ADDR 0x4000 // xdata xBUS start address
|
1217 | #define XDATA_XBUS_CS0 0x4000 // xdata xBUS chip-selection 0#
|
1218 | #define XDATA_XCS0_SIZE 0x4000 // size of xdata xBUS chip-selection 0#: @0x4000~0x7FFF
|
1219 | #define XDATA_XBUS_CS1 0x8000 // xdata xBUS chip-selection 1#
|
1220 | #define XDATA_XCS1_SIZE 0x8000 // size of xdata xBUS chip-selection 1#: @0x8000~0xFFFF
|
1221 |
|
1222 | /* USB auxiliary Registers on xDATA, xSFR */
|
1223 | #define REG_USB_AUX_BASE 0x2440 // USB auxiliary registers base address
|
1224 | extern unsigned char volatile __xdata UEP4_1_MOD;
|
1225 | extern unsigned char volatile __pdata pUEP4_1_MOD;
|
1226 | #define bUEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
|
1227 | #define bUEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
|
1228 | #define bUEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
|
1229 | // bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
|
1230 | // 0 0 x: disable endpoint and disable buffer
|
1231 | // 1 0 0: 64 bytes buffer for receiving (OUT endpoint)
|
1232 | // 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
|
1233 | // 0 1 0: 64 bytes buffer for transmittal (IN endpoint)
|
1234 | // 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
|
1235 | // 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
|
1236 | // 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
|
1237 | #define bUEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
|
1238 | #define bUEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
|
1239 | // bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
|
1240 | // 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
|
1241 | // 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
|
1242 | // 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
|
1243 | // 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
|
1244 | // + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
|
1245 | extern unsigned char volatile __xdata UEP2_3_MOD;
|
1246 | extern unsigned char volatile __pdata pUEP2_3_MOD;
|
1247 | #define bUEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
|
1248 | #define bUEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
|
1249 | #define bUEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
|
1250 | #define bUEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
|
1251 | #define bUEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
|
1252 | #define bUEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
|
1253 | //unsigned short volatile xdata UEP0_DMA _at_ 0x2448; // endpoint 0&4 buffer start address, must even address, big-endian
|
1254 | extern unsigned char volatile __xdata UEP0_DMA_H;
|
1255 | extern unsigned char volatile __xdata UEP0_DMA_L;
|
1256 | extern unsigned char volatile __pdata pUEP0_DMA_H;
|
1257 | extern unsigned char volatile __pdata pUEP0_DMA_L;
|
1258 | //unsigned short volatile xdata UEP1_DMA _at_ 0x244A; // endpoint 1 buffer start address, must even address, big-endian
|
1259 | extern unsigned char volatile __xdata UEP1_DMA_H;
|
1260 | extern unsigned char volatile __xdata UEP1_DMA_L;
|
1261 | extern unsigned char volatile __pdata pUEP1_DMA_H;
|
1262 | extern unsigned char volatile __pdata pUEP1_DMA_L;
|
1263 | //unsigned short volatile xdata UEP2_DMA _at_ 0x244C; // endpoint 2 buffer start address, must even address, big-endian
|
1264 | extern unsigned char volatile __xdata UEP2_DMA_H;
|
1265 | extern unsigned char volatile __xdata UEP2_DMA_L;
|
1266 | extern unsigned char volatile __pdata pUEP2_DMA_H;
|
1267 | extern unsigned char volatile __pdata pUEP2_DMA_L;
|
1268 | //unsigned short volatile xdata UEP3_DMA _at_ 0x244E; // endpoint 3 buffer start address, must even address, big-endian
|
1269 | extern unsigned char volatile __xdata UEP3_DMA_H;
|
1270 | extern unsigned char volatile __xdata UEP3_DMA_L;
|
1271 | extern unsigned char volatile __pdata pUEP3_DMA_H;
|
1272 | extern unsigned char volatile __pdata pUEP3_DMA_L;
|
1273 | //UINT8XV UH_EP_MOD _at_ 0x2447; // host endpoint mode
|
1274 | #define UH_EP_MOD UEP2_3_MOD
|
1275 | #define pUH_EP_MOD pUEP2_3_MOD
|
1276 | #define bUH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
|
1277 | #define bUH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
|
1278 | // bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
|
1279 | // 0 x: disable endpoint and disable buffer
|
1280 | // 1 0: 64 bytes buffer for transmittal (OUT endpoint)
|
1281 | // 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
|
1282 | #define bUH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
|
1283 | #define bUH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
|
1284 | // bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
|
1285 | // 0 x: disable endpoint and disable buffer
|
1286 | // 1 0: 64 bytes buffer for receiving (IN endpoint)
|
1287 | // 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
|
1288 | //unsigned short volatile xdata UH_RX_DMA _at_ 0x244C; // host rx endpoint buffer start address, big-endian
|
1289 | #define UH_RX_DMA UEP2_DMA
|
1290 | #define pUH_RX_DMA pUEP2_DMA
|
1291 | //UINT8XV UH_RX_DMA_H _at_ 0x244C; // host rx endpoint buffer start address high byte
|
1292 | #define UH_RX_DMA_H UEP2_DMA_H
|
1293 | #define pUH_RX_DMA_H pUEP2_DMA_H
|
1294 | //UINT8XV UH_RX_DMA_L _at_ 0x244D; // host rx endpoint buffer start address low byte
|
1295 | #define UH_RX_DMA_L UEP2_DMA_L
|
1296 | #define pUH_RX_DMA_L pUEP2_DMA_L
|
1297 | //unsigned short volatile xdata UH_TX_DMA _at_ 0x244E; // host tx endpoint buffer start address, big-endian
|
1298 | #define UH_TX_DMA UEP3_DMA
|
1299 | #define pUH_TX_DMA pUEP3_DMA
|
1300 | //UINT8XV UH_TX_DMA_H _at_ 0x244E; // host tx endpoint buffer start address high byte
|
1301 | #define UH_TX_DMA_H UEP3_DMA_H
|
1302 | #define pUH_TX_DMA_H pUEP3_DMA_H
|
1303 | //UINT8XV UH_TX_DMA_L _at_ 0x244F; // host tx endpoint buffer start address low byte
|
1304 | #define UH_TX_DMA_L UEP3_DMA_L
|
1305 | #define pUH_TX_DMA_L pUEP3_DMA_L
|
1306 |
|
1307 | /* LED Registers on xDATA, xSFR */
|
1308 | #define REG_LED_BASE 0x2880 // LED registers base address
|
1309 | extern unsigned char volatile __xdata LED_STAT;
|
1310 | extern unsigned char volatile __pdata pLED_STAT;
|
1311 |
|
1312 | #define bLED_IF_DMA_END 0x80 // interrupt flag for DMA completion, write 1 to clear or write LED_DMA_CN to clear
|
1313 | #define bLED_FIFO_EMPTY 0x40 // ReadOnly: indicate FIFO empty status
|
1314 | #define bLED_IF_FIFO_REQ 0x20 // interrupt flag for request FIFO data ( FIFO <=2), write 1 to clear
|
1315 | #define bLED_CLOCK 0x10 // ReadOnly: current LED clock level
|
1316 | #define MASK_LED_FIFO_CNT 0x07 // ReadOnly: bit mask of LED FIFO count
|
1317 |
|
1318 | extern unsigned char volatile __xdata LED_CTRL;
|
1319 | extern unsigned char volatile __pdata pLED_CTRL;
|
1320 |
|
1321 | #define bLED_CHAN_MOD1 0x80 // LED channel mode high bit
|
1322 | #define bLED_CHAN_MOD0 0x40 // LED channel mode low bit
|
1323 | #define MASK_LED_CHAN_MOD 0xC0 // bit mask of LED channel mode
|
1324 | // bLED_CHAN_MOD1 & bLED_CHAN_MOD0: LED channel mode
|
1325 | // 00: single channel output, LED0
|
1326 | // 01: dual channels output, LED0/1
|
1327 | // 10: 4 channels output, LED0~3
|
1328 | // 11: 4 channels output and LED2/3 from aux buffer, LED0~3
|
1329 | #define bLED_IE_FIFO_REQ 0x20 // enable interrupt for FIFO <=2
|
1330 | #define bLED_DMA_EN 0x10 // DMA enable and DMA interrupt enable for LED
|
1331 | #define bLED_OUT_EN 0x08 // LED output enable
|
1332 | #define bLED_OUT_POLAR 0x04 // LED output polarity: 0=pass, 1=invert
|
1333 | #define bLED_CLR_ALL 0x02 // force clear FIFO and count of LED
|
1334 | #define bLED_BIT_ORDER 0x01 // LED bit data order: 0=LSB first, 1=MSB first
|
1335 |
|
1336 | extern unsigned char volatile __xdata LED_DATA;
|
1337 | extern unsigned char volatile __pdata pLED_DATA;
|
1338 |
|
1339 | //UINT8XV LED_FIFO_CN _at_ 0x2882; // ReadOnly: FIFO count status
|
1340 | #define LED_FIFO_CN LED_DATA
|
1341 |
|
1342 | extern unsigned char volatile __xdata LED_CK_SE;
|
1343 | extern unsigned char volatile __pdata pLED_CK_SE;
|
1344 |
|
1345 | //unsigned short volatile xdata LED_DMA _at_ 0x2884; // DMA address, must even address, big-endian, automatic increasing after DMA
|
1346 | extern unsigned char volatile __xdata LED_DMA_AH;
|
1347 | extern unsigned char volatile __xdata LED_DMA_AL;
|
1348 | extern unsigned char volatile __pdata pLED_DMA_AH;
|
1349 | extern unsigned char volatile __pdata pLED_DMA_AL;
|
1350 |
|
1351 | extern unsigned char volatile __xdata LED_DMA_CN;
|
1352 | extern unsigned char volatile __pdata pLED_DMA_CN;
|
1353 | //unsigned short volatile xdata LED_DMA_X _at_ 0x2888; // aux buffer DMA address, must even address, big-endian, automatic increasing after DMA
|
1354 |
|
1355 | extern unsigned char volatile __xdata LED_DMA_XH;
|
1356 | extern unsigned char volatile __xdata LED_DMA_XL;
|
1357 | extern unsigned char volatile __pdata pLED_DMA_XH;
|
1358 | extern unsigned char volatile __pdata pLED_DMA_XL;
|
1359 |
|
1360 |
|
1361 |
|
1362 |
|
1363 | /*----- Reference Information --------------------------------------------*/
|
1364 | #define ID_CH559 0x59 // chip ID
|
1365 |
|
1366 | /* Interrupt routine address and interrupt number */
|
1367 | #define INT_ADDR_INT0 0x0003 // interrupt vector address for INT0 or LED
|
1368 | #define INT_ADDR_TMR0 0x000B // interrupt vector address for timer0
|
1369 | #define INT_ADDR_INT1 0x0013 // interrupt vector address for INT1
|
1370 | #define INT_ADDR_TMR1 0x001B // interrupt vector address for timer1
|
1371 | #define INT_ADDR_UART0 0x0023 // interrupt vector address for UART0
|
1372 | #define INT_ADDR_TMR2 0x002B // interrupt vector address for timer2
|
1373 | #define INT_ADDR_SPI0 0x0033 // interrupt vector address for SPI0
|
1374 | #define INT_ADDR_TMR3 0x003B // interrupt vector address for timer3
|
1375 | #define INT_ADDR_USB 0x0043 // interrupt vector address for USB
|
1376 | #define INT_ADDR_ADC 0x004B // interrupt vector address for ADC
|
1377 | #define INT_ADDR_UART1 0x0053 // interrupt vector address for UART1
|
1378 | #define INT_ADDR_PWM1 0x005B // interrupt vector address for PWM1
|
1379 | #define INT_ADDR_GPIO 0x0063 // interrupt vector address for GPIO
|
1380 | #define INT_ADDR_WDOG 0x006B // interrupt vector address for watch-dog timer
|
1381 |
|
1382 | #define INT_NO_INT0 0 // interrupt number for INT0 or LED
|
1383 | #define INT_NO_TMR0 1 // interrupt number for timer0
|
1384 | #define INT_NO_INT1 2 // interrupt number for INT1
|
1385 | #define INT_NO_TMR1 3 // interrupt number for timer1
|
1386 | #define INT_NO_UART0 4 // interrupt number for UART0
|
1387 | #define INT_NO_TMR2 5 // interrupt number for timer2
|
1388 | #define INT_NO_SPI0 6 // interrupt number for SPI0
|
1389 | #define INT_NO_TMR3 7 // interrupt number for timer3
|
1390 | #define INT_NO_USB 8 // interrupt number for USB
|
1391 | #define INT_NO_ADC 9 // interrupt number for ADC
|
1392 | #define INT_NO_UART1 10 // interrupt number for UART1
|
1393 | #define INT_NO_PWM1 11 // interrupt number for PWM1
|
1394 | #define INT_NO_GPIO 12 // interrupt number for GPIO
|
1395 | #define INT_NO_WDOG 13 // interrupt number for watch-dog timer
|
1396 |
|
1397 | /* Special Program Space */
|
1398 | #define DATA_FLASH_ADDR 0xF000 // start address of Data-Flash
|
1399 | #define BOOT_LOAD_ADDR 0xF400 // start address of boot loader program
|
1400 | #define ROM_CFG_ADDR 0xFFFE // chip configuration information address
|
1401 |
|
1402 | /*
|
1403 | New Instruction: MOVX @DPTR1,A
|
1404 | Instruction Code: 0xA5
|
1405 | Instruction Cycle: 1
|
1406 | Instruction Operation:
|
1407 | step-1. write ACC @DPTR1 into xdata SRAM embedded chip
|
1408 | step-2. increase DPTR1
|
1409 | ASM example:
|
1410 | INC XBUS_AUX
|
1411 | MOV DPTR,#TARGET_ADDR ;DPTR1
|
1412 | DEC XBUS_AUX
|
1413 | MOV DPTR,#SOURCE_ADDR ;DPTR0
|
1414 | MOV R7,#xxH
|
1415 | LOOP: MOVX A,@DPTR ;DPTR0
|
1416 | INC DPTR ;DPTR0, if need
|
1417 | DB 0A5H ;MOVX @DPTR1,A & INC DPTR1
|
1418 | DJNZ R7,LOOP
|
1419 | */
|
1420 | #pragma language=restore
|
1421 |
|
1422 | #endif // _CH559_IAR_H_
|