1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL;
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4 |
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5 | entity Auslesen is Port(
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6 | CLK100: in std_logic;
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7 | -- ADC Signale?
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8 | UART_RX: in std_logic;
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9 | UART_TX: out std_logic);
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10 | end Auslesen;
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11 |
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12 | architecture Behavioral of Auslesen is
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13 |
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14 | component uart is
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15 | generic(
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16 | clk_freq: integer;
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17 | baudrate: integer);
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18 | Port (
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19 | clk : in std_logic;
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20 | start_snd: in std_logic;
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21 | start_rcv: out std_logic;
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22 | byte_snd : in std_logic_vector(7 downto 0);
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23 | byte_rcv : out std_logic_vector(7 downto 0);
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24 | tx : out std_logic;
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25 | rx : in std_logic;
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26 | ready : out std_logic);
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27 | end component;
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28 |
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29 | -- component ADC is ...
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30 |
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31 | signal ADC_data_ready: std_logic:='0';
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32 | signal ADC_data: std_logic_vector(15 downto 0):=(others => '0');
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33 |
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34 | --------------------------------------- FSM Control --------------
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35 | type s_control_type is(s_wait, s_fill_sample, s_send_wait_one, s_send_samples_l, s_send_samples_h);
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36 | signal s_control: s_control_type:= s_wait;
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37 | --------------------------------------- FSM Send UART ------------
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38 | type Sample_Array is array (0 to 2**15-1) of std_logic_vector(15 downto 0);
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39 | signal Sample_Arr : Sample_Array := (others => x"0000");
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40 | signal Sample_Addr: integer range 0 to 2**13-1:=0;
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41 | signal ADC_select: integer range 0 to 15:=0;
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42 | signal Sample_len2hoch: integer range 8 to 15:=10;
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43 | signal Sample_from_RAM: std_logic_vector(15 downto 0):=(others => '0');
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44 | -------------------------- UART -------------------------------------
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45 | signal UART_start_snd: std_logic:='0';
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46 | signal UART_start_rcv: std_logic:='0';
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47 | signal UART_byte_snd: std_logic_vector(7 downto 0):="00000000";
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48 | signal UART_byte_rcv: std_logic_vector(7 downto 0):="00000000";
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49 | signal UART_ready: std_logic:='0';
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50 |
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51 | begin
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52 |
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53 | UART_0: uart
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54 | generic map(
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55 | clk_freq => 100000000,
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56 | baudrate => 9600)
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57 | port map(
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58 | clk => CLK100,
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59 | start_snd => UART_start_snd,
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60 | start_rcv => UART_start_rcv,
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61 | byte_snd => UART_byte_snd,
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62 | byte_rcv => UART_byte_rcv,
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63 | tx => UART_TX,
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64 | rx => UART_RX,
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65 | ready => UART_ready);
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66 |
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67 | ------------------------- FSM -----------------------------------------------------------
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68 | process begin
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69 | wait until rising_edge(CLK100);
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70 | UART_start_snd <= '0';
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71 | Sample_from_RAM <= Sample_Arr(Sample_Addr);
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72 | if s_control = s_wait then
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73 | if UART_start_rcv = '1' then
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74 | s_control <= s_fill_sample;
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75 | Sample_Addr <= 0;
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76 |
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77 | ADC_select <= to_integer(unsigned(UART_byte_rcv(3 downto 0)));
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78 | if unsigned(UART_byte_rcv(7 downto 4)) > 7 then
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79 | Sample_len2hoch <= to_integer(unsigned(UART_byte_rcv(7 downto 4)));
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80 | else
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81 | Sample_len2hoch <= 8;
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82 | end if;
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83 | end if;
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84 | elsif s_control = s_fill_sample then
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85 | if ADC_select = 0 and ADC_data_ready = '1' then
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86 | Sample_Arr(Sample_Addr) <= ADC_data;
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87 | if Sample_Addr < 2**Sample_len2hoch-1 then
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88 | Sample_Addr <= Sample_Addr +1;
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89 | else
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90 | Sample_Addr <= 0;
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91 | s_control <= s_send_wait_one;
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92 | end if;
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93 | -- elsif ADC_select = 1, ...
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94 | end if;
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95 | elsif s_control = s_send_wait_one then
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96 | s_control <= s_send_samples_h;
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97 | elsif s_control = s_send_samples_h then
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98 | if UART_ready = '1' then
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99 | UART_byte_snd <= Sample_from_RAM(15 downto 8);
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100 | UART_start_snd <= '1';
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101 | s_control <= s_send_samples_l;
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102 | end if;
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103 | elsif s_control = s_send_samples_l then
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104 | if UART_ready = '1' then
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105 | UART_byte_snd <= Sample_from_RAM(7 downto 0);
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106 | UART_start_snd <= '1';
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107 | if Sample_Addr < 2**Sample_len2hoch-1 then
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108 | Sample_Addr <= Sample_Addr +1;
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109 | s_control <= s_send_samples_h;
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110 | else
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111 | Sample_Addr <= 0;
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112 | s_control <= s_wait;
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113 | end if;
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114 | end if;
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115 | end if;
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116 | end process;
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117 |
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118 | end Behavioral;
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