tb_PWM.vhd

-------------------------------------------------------------------------------

--                                                                      

--                        Projekt

--  

-------------------------------------------------------------------------------

--                                                                      

-- ENTITY:         tb_dezcntr

--

-- FILENAME:       tb_dezcntr.vhd

-- 

-- ARCHITECTURE:   struc

-- 

-- ENGINEER:       Wolfgang Gartner

--

-- DATE:           30.03.2009

--

-- VERSION:        1.0

--

-------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

entity tb_PWM is end tb_PWM;

architecture sim of tb_PWM is

-- Declaration of the component under test

component PWM

port (

      data_i: in std_logic_vector (7 downto 0);

      v_o: out std_logic;

      pause_i: in std_logic;

      play_i: in std_logic;

      stop_i: in std_logic;

      eof_i: in std_logic;

      led : out std_logic_vector(7 downto 0); -- value for LEDs

      clk_i: in std_logic;

      reset_n: in std_logic

     );

end component;

signal data_i: std_logic_vector (7 downto 0);

signal v_o: std_logic;

signal pause_i: std_logic;

signal play_i: std_logic;

signal stop_i: std_logic;

signal eof_i: std_logic;

signal led : std_logic_vector(7 downto 0); -- value for LEDs

signal clk_i: std_logic := '1';

signal reset_n: std_logic := '1';

begin

clk_i <= not clk_i after 10 ns; -- 1/2 Periodendauer = Wechsel

reset_n <= '0' after 10 ns;

-- Instantiate the design under test

i_PWM : PWM

port map 

(     data_i => data_i,

      v_o => v_o,

      pause_i => pause_i,

      play_i => play_i,

      stop_i => stop_i,

      eof_i => eof_i,

      led  => led,

      clk_i => clk_i,

      reset_n => reset_n

 );

-- Generate inputs for simulation

run : process

begin

data_i <= (others => '0');

pause_i <= '0';

play_i <= '0';

stop_i <= '0';

eof_i <= '0';

led  <= (others => '1');

wait for 10 ns;

data_i <= (others => '0');

play_i <= '1';

wait for 1000 ns;

data_i <= "01011100" ;

play_i <= '0';

stop_i <= '1';

wait for 100 ns;

end process run;

end sim;