1 | -- ---------------------------------------------------------------------
|
2 | -- @file : arbitration.vhd
|
3 | -- ---------------------------------------------------------------------
|
4 | --
|
5 | -- Author: Klaus Schleisiek
|
6 | -- Last change: KS 11.03.2021 18:32:52
|
7 | -- Project : arbitration test
|
8 | -- Language : VHDL-2008
|
9 | --
|
10 | -- ---------------------------------------------------------------------
|
11 | LIBRARY IEEE;
|
12 | USE IEEE.STD_LOGIC_1164.ALL;
|
13 | USE IEEE.NUMERIC_STD.ALL;
|
14 |
|
15 | ENTITY bench IS
|
16 | END bench;
|
17 |
|
18 | ARCHITECTURE testbench OF bench IS
|
19 |
|
20 | SIGNAL clk, clk_en : STD_LOGIC;
|
21 | SIGNAL reset : STD_LOGIC;
|
22 |
|
23 | SIGNAL req1, req2, req3 : STD_LOGIC;
|
24 | SIGNAL grant1, grant2, grant3 : STD_LOGIC; -- synchronous grant output
|
25 |
|
26 | BEGIN
|
27 |
|
28 | reset <= '1', '0' AFTER 100 ns;
|
29 |
|
30 | clk_en <= '0' WHEN (req1 AND grant1) = '1' OR (req2 AND grant2) = '1' OR (req3 AND grant3) = '1' ELSE '1';
|
31 |
|
32 | arbitrator: PROCESS (clk, reset)
|
33 | BEGIN
|
34 | IF reset = '1' THEN
|
35 | grant1 <= '0';
|
36 | grant2 <= '0';
|
37 | grant3 <= '0';
|
38 | ELSIF rising_edge(clk) THEN
|
39 | IF clk_en = '1' THEN
|
40 | IF req1 = '1' THEN
|
41 | grant1 <= '1';
|
42 | ELSIF req2 = '1' THEN
|
43 | grant2 <= '1';
|
44 | ELSIF req3 = '1' THEN
|
45 | grant3 <= '1';
|
46 | END IF;
|
47 | END IF;
|
48 | IF req1 = '0' THEN
|
49 | grant1 <= '0';
|
50 | END IF;
|
51 | IF req2 = '0' THEN
|
52 | grant2 <= '0';
|
53 | END IF;
|
54 | IF req3 = '0' THEN
|
55 | grant3 <= '0';
|
56 | END IF;
|
57 | END IF;
|
58 | END PROCESS arbitrator;
|
59 |
|
60 | parallel_proc1: PROCESS
|
61 | BEGIN
|
62 | req1 <= '0';
|
63 | WAIT FOR 270 ns;
|
64 | req1 <= '1';
|
65 | WAIT UNTIL grant1 <= '1';
|
66 | WAIT FOR 40 ns;
|
67 | req1 <= '0';
|
68 | WAIT FOR 150 ns;
|
69 | req1 <= '1';
|
70 | WAIT UNTIL grant1 <= '1';
|
71 | WAIT FOR 40 ns;
|
72 | req1 <= '0';
|
73 | WAIT;
|
74 | END PROCESS parallel_proc1;
|
75 |
|
76 | parallel_proc2: PROCESS
|
77 | BEGIN
|
78 | req2 <= '0';
|
79 | WAIT FOR 280 ns;
|
80 | req2 <= '1';
|
81 | WAIT UNTIL grant2 <= '1';
|
82 | WAIT FOR 160 ns;
|
83 | req2 <= '0';
|
84 | WAIT;
|
85 | END PROCESS parallel_proc2;
|
86 |
|
87 | parallel_proc3: PROCESS
|
88 | BEGIN
|
89 | req3 <= '0';
|
90 | WAIT FOR 350 ns;
|
91 | req3 <= '1';
|
92 | WAIT UNTIL grant3 <= '1';
|
93 | WAIT FOR 40 ns;
|
94 | req3 <= '0';
|
95 | WAIT;
|
96 | END PROCESS parallel_proc3;
|
97 |
|
98 | oscillator: PROCESS
|
99 | BEGIN
|
100 | clk <= '0';
|
101 | WAIT FOR 150 ns;
|
102 | LOOP
|
103 | WAIT FOR 50 ns;
|
104 | clk <= '1';
|
105 | WAIT FOR 50 ns;
|
106 | clk <= '0';
|
107 | END LOOP;
|
108 | END PROCESS oscillator;
|
109 |
|
110 | END testbench;
|