1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 | entity counter is
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5 | generic ( sys_clk :INTEGER := 50_000_000;
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6 | periode : time := 40.0 ns;
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7 | resolution : natural:= 5;
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8 | n_Bit : natural:= 10);
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9 |
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10 | port( clk_in, n_reset : in std_logic;
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11 | Upwm0 : in std_logic_vector(n_Bit-6 downto 0); -- 5 Bit for parallel load
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12 | Upwm1 : in std_logic_vector(n_Bit-1 downto 5); -- 5 Bit for parallel load
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13 | Upwm0_out : out std_logic_vector(n_Bit-6 downto 0); -- 5 Bit for parallel load
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14 | Upwm1_out : out std_logic_vector(n_Bit-1 downto 5)); -- 5 Bit for parallel load
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15 |
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16 | end entity counter;
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17 |
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18 | architecture counter_a of counter is
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19 | signal pwm0 :unsigned(n_Bit-6 downto 0):=(others=> '0');
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20 | signal pwm1 :unsigned(n_Bit-1 downto 5):=(others=> '0');
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21 |
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22 |
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23 | begin
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24 | count: process(clk_in,n_reset)--sensitivity list
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25 | begin
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26 | if(n_reset = '0') then
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27 | pwm0 <= unsigned(Upwm0);
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28 | pwm1 <= unsigned(Upwm1);
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29 |
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30 | else
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31 | if(rising_edge(clk_in)) then
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32 | if(pwm0 < to_unsigned(31,n_Bit))then-- pwm1 < to_unsigned(31,n_Bit))then
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33 | pwm0<= (pwm0 + 1);
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34 | --pwm1<= (pwm1 + 1);
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35 | else
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36 | pwm0 <= unsigned(Upwm0);
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37 | --pwm1 <= unsigned(Upwm1);
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38 | end if; -- pwm0&1
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39 | end if; -- rising_edge
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40 | end if; -- reset
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41 | end process count;
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42 |
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43 | output:
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44 | Upwm0_out <= std_logic_vector(pwm0);
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45 | Upwm1_out <= std_logic_vector(pwm1);
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46 |
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47 | end architecture counter_a;
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