1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 | entity counter is
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5 | generic ( n_Bit : natural:= 10);
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6 |
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7 | port( clk_in, n_reset : in std_logic;
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8 | Upwm0 : in std_logic_vector(n_Bit-6 downto 0); -- 5 Bit for parallel load
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9 | Upwm1 : in std_logic_vector(n_Bit-1 downto 4); -- 5 Bit for parallel load
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10 | Upwm0_out : out std_logic
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11 | );
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12 |
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13 | end entity counter;
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14 |
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15 | architecture counter_a of counter is
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16 | signal pwm0 :unsigned(n_Bit-6 downto 0):= (others=>'0');
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17 | signal pwm1 :unsigned(n_Bit-1 downto 4):= (others=>'0');
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18 | signal pwm_control :std_logic:='0';
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19 | signal pwm :std_logic:='0';
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20 |
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21 | begin
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22 | count: process(clk_in,n_reset)--sensitivity list
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23 | begin
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24 | if(n_reset = '0') then
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25 | pwm0 <= unsigned(Upwm0);
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26 | pwm_control <= '0';
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27 |
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28 | else
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29 | if(rising_edge(clk_in)) then
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30 | if(pwm0 < to_unsigned(31,n_Bit)) then
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31 | pwm0 <= (pwm0 + 1);
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32 | pwm_control <= '1';
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33 | else if(pwm0 > to_unsigned(0,n_Bit))then
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34 | pwm0 <= (pwm0 - 1);
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35 | pwm_control <='0';
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36 | end if;--pwm0 fall
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37 | end if; -- pwm0 rise
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38 | end if; -- rising_edge
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39 | end if; -- reset
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40 | end process count;
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41 |
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42 | pwm_logic:process(clk_in)
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43 | begin
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44 | if(rising_edge(clk_in)) then
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45 | if(pwm0 => Upwm0) then
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46 | pwm <= '1';
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47 | else
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48 | pwm <= '0';
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49 | end if;
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50 | end if;
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51 | end process pwm_logic;
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52 | output:
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53 | Upwm0_out <= std_logic(pwm);
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54 |
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55 |
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56 | end architecture counter_a;
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