1 | --Eskandari, 30.03.2021
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2 | -- 5Bit Phase Correct PWM
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3 | --
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4 |
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5 | library ieee;
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6 | use ieee.std_logic_1164.all;
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7 | use ieee.numeric_std.all;
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8 | entity counter is
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9 | generic ( n_Bit : natural:= 10);
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10 |
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11 | port( clk_in, n_reset : in std_logic
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12 | Upwm0 : in std_logic_vector(n_Bit-1 downto 0);
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13 | pwm0_out : out std_logic;
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14 | pwm1_out : out std_logic;
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15 | );
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16 |
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17 | end entity counter;
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18 |
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19 | architecture counter_a of counter is
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20 | signal pwm0 :unsigned(n_Bit-6 downto 0):= (others=>'0');
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21 | signal pwm1 :unsigned(n_Bit-1 downto 4):= (others=>'0');
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22 | signal pwm_control :std_logic:='0';
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23 | signal pwm :std_logic:='0';
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24 |
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25 | begin
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26 | count: process(clk_in,n_reset)--sensitivity list
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27 | begin
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28 | if(n_reset = '0') then
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29 | pwm0 <= unsigned(Upwm0);
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30 | pwm_control <= '0';
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31 |
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32 | else
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33 | if(rising_edge(clk_in)) then
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34 | if(pwm0 < to_unsigned(31,n_Bit)) then
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35 | pwm0 <= (pwm0 + 1);
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36 | pwm_control <= '1';
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37 | else if(pwm0 > to_unsigned(0,n_Bit))then
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38 | pwm0 <= (pwm0 - 1);
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39 | pwm_control <='0';
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40 | end if;--pwm0 fall
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41 | end if; -- pwm0 rise
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42 | end if; -- rising_edge
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43 | end if; -- reset
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44 | end process count;
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45 |
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46 | pwm_logic:process(clk_in)
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47 | begin
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48 | if(rising_edge(clk_in)) then
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49 | if(pwm0 => Upwm0) then
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50 | pwm <= '1';
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51 | else
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52 | pwm <= '0';
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53 | end if;
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54 | end if;
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55 | end process pwm_logic;
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56 | output:
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57 | Upwm0_out <= std_logic(pwm);
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58 |
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59 |
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60 | end architecture counter_a;
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