PWM.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity PWM is

  Port(

  clock    : in std_logic;

  schalter : in  std_logic_vector(9 downto 0); -- nutze schalter(9 downto 5) für die PWM_1 und schalter(4 downto 0)für die PWM_0

  PWM_0    : out std_logic;

  PWM_1    : out std_logic);

end PWM;

architecture rtl of PWM is

-- Signale hierher

 signal count:     unsigned (5 downto 0) := (others=>'0');

 signal countout:  integer range 0 to 31;

 signal PWM_out  :  std_logic :='0';

begin

-- hier ungetaktete Kombinatorik

count <= count+1 when rising_edge(clock) ; 

countout <= to_integer(count)  when count(5)='0' else

              31-to_integer(count(4 downto 0));

PWM_out <= '0' when count(5)= '0' else '1';

--process begin

  --wait until rising_edge(clock);

  -- getaktete Beschreibung hier

--end process;

-- ungetaktete Kombinatorik darf auch hier stehen

end;