PWM_tb.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity tb_PWM is

end tb_PWM;

architecture tb of tb_PWM is

component PWM is

  Port(

  clock    : in std_logic;

  schalter : in  std_logic_vector(9 downto 0);

  PWM_0    : out std_logic;

  PWM_1    : out std_logic);

end component;

signal clock    : std_logic:='0';

signal schalter : std_logic_vector(9 downto 0):=(others => '0');

signal PWM_0    : std_logic:='0';

signal PWM_1    : std_logic:='0';

signal breite_0 : integer range 0 to 31:=0;

signal breite_1 : integer range 0 to 31:=0;

begin

clock <= not clock after 10 ns;

schalter <= std_logic_vector(to_unsigned(breite_1,5)) & std_logic_vector(to_unsigned(breite_0,5));

process begin

  breite_0 <= 10;

  breite_1 <= 16;

  wait for 10 us;

  breite_0 <= 23;

  breite_1 <= 9;

  wait for 10 us;

  breite_0 <= 31;

  breite_1 <= 0;

  wait;

end process;

uut: PWM

  Port Map(

  clock    => clock,

  schalter => schalter,

  PWM_0    => PWM_0,

  PWM_1    => PWM_1);

end;