1 | #ifndef __msp430x22x4
|
2 | #define __msp430x22x4
|
3 |
|
4 | /* msp430x22x4.h
|
5 | *
|
6 | * mspgcc project: MSP430 device headers
|
7 | * MSP430x22x4 family header
|
8 | *
|
9 | * (c) 2005 by Steve Underwood <steveu@coppice.org>
|
10 | * Originally based in part on work by Texas Instruments Inc.
|
11 | *
|
12 | * $Id: msp430x22x4.h,v 1.7 2008/06/18 00:54:02 cliechti Exp $
|
13 | */
|
14 |
|
15 | #include <iomacros.h>
|
16 |
|
17 | #define __MSP430_HAS_ADC10__
|
18 | #define __MSP430_HAS_WDT__
|
19 | #define __MSP430_HAS_PORT1_R__
|
20 | #define __MSP430_HAS_PORT2_R__
|
21 | #define __MSP430_HAS_PORT3_R__
|
22 | #define __MSP430_HAS_PORT4_R__
|
23 | #define __MSP430_HAS_TA3__
|
24 | #define __MSP430_HAS_TB3__
|
25 | #define __MSP430_HAS_BC2__
|
26 | #define __MSP430_HAS_FLASH2__
|
27 | #define __MSP430_HAS_OA_2__
|
28 | #define __MSP430_HAS_USCI__
|
29 |
|
30 | #define __msp430_have_opamp_1
|
31 | #define __msp430_have_opamp_output_select
|
32 | #define __msp430_have_adc10ae2
|
33 |
|
34 | #include <msp430/basic_clock.h>
|
35 | #include <msp430/flash.h>
|
36 | #include <msp430/eprom.h>
|
37 | #include <msp430/timera.h>
|
38 | #include <msp430/timerb.h>
|
39 | #include <msp430/gpio.h>
|
40 | #include <msp430/adc10.h>
|
41 | #include <msp430/opamp.h>
|
42 | #include <msp430/usci.h>
|
43 |
|
44 | #include <msp430/common.h>
|
45 |
|
46 | #define IE1_ 0x0000 /* Interrupt Enable 1 */
|
47 | sfrb(IE1, IE1_);
|
48 | #define WDTIE (1<<0) /* Watchdog Interrupt Enable */
|
49 | #define OFIE (1<<1) /* Osc. Fault Interrupt Enable */
|
50 | #define NMIIE (1<<4) /* NMI Interrupt Enable */
|
51 | #define ACCVIE (1<<5) /* Flash Access Violation Interrupt Enable */
|
52 |
|
53 | #define IFG1_ 0x0002 /* Interrupt Flag 1 */
|
54 | sfrb(IFG1, IFG1_);
|
55 | #define WDTIFG (1<<0) /* Watchdog Interrupt Flag */
|
56 | #define OFIFG (1<<1) /* Osc. Fault Interrupt Flag */
|
57 | #define PORIFG (1<<2) /* Power On Interrupt Flag */
|
58 | #define RSTIFG (1<<3) /* Reset Interrupt Flag */
|
59 | #define NMIIFG (1<<4) /* NMI Interrupt Flag */
|
60 |
|
61 | #define IE2_ 0x0001 /* Interrupt Enable 2 */
|
62 | sfrb(IE2, IE2_);
|
63 | #define UCA0RXIE (1<<0)
|
64 | #define UCA0TXIE (1<<1)
|
65 | #define UCB0RXIE (1<<2)
|
66 | #define UCB0TXIE (1<<3)
|
67 |
|
68 | #define IFG2_ 0x0003 /* Interrupt Flag 2 */
|
69 | sfrb(IFG2,IFG2_);
|
70 | #define UCA0RXIFG (1<<0)
|
71 | #define UCA0TXIFG (1<<1)
|
72 | #define UCB0RXIFG (1<<2)
|
73 | #define UCB0TXIFG (1<<3)
|
74 |
|
75 | /************************************************************
|
76 | * Calibration Data in Info Mem
|
77 | ************************************************************/
|
78 |
|
79 | #ifndef __DisableCalData
|
80 |
|
81 | #define CALDCO_16MHZ_ 0x10F8 /* DCOCTL Calibration Data for 16MHz */
|
82 | sfrb(CALDCO_16MHZ, CALDCO_16MHZ_);
|
83 | #define CALBC1_16MHZ_ 0x10F9 /* BCSCTL1 Calibration Data for 16MHz */
|
84 | sfrb(CALBC1_16MHZ, CALBC1_16MHZ_);
|
85 | #define CALDCO_12MHZ_ 0x10FA /* DCOCTL Calibration Data for 12MHz */
|
86 | sfrb(CALDCO_12MHZ, CALDCO_12MHZ_);
|
87 | #define CALBC1_12MHZ_ 0x10FB /* BCSCTL1 Calibration Data for 12MHz */
|
88 | sfrb(CALBC1_12MHZ, CALBC1_12MHZ_);
|
89 | #define CALDCO_8MHZ_ 0x10FC /* DCOCTL Calibration Data for 8MHz */
|
90 | sfrb(CALDCO_8MHZ, CALDCO_8MHZ_);
|
91 | #define CALBC1_8MHZ_ 0x10FD /* BCSCTL1 Calibration Data for 8MHz */
|
92 | sfrb(CALBC1_8MHZ, CALBC1_8MHZ_);
|
93 | #define CALDCO_1MHZ_ 0x10FE /* DCOCTL Calibration Data for 1MHz */
|
94 | sfrb(CALDCO_1MHZ, CALDCO_1MHZ_);
|
95 | #define CALBC1_1MHZ_ 0x10FF /* BCSCTL1 Calibration Data for 1MHz */
|
96 | sfrb(CALBC1_1MHZ, CALBC1_1MHZ_);
|
97 |
|
98 | #endif /* #ifndef __DisableCalData */
|
99 |
|
100 | #define PORT1_VECTOR 4 /* 0xFFE4 Port 1 */
|
101 | #define PORT2_VECTOR 6 /* 0xFFE6 Port 2 */
|
102 | #define ADC10_VECTOR 10 /* 0xFFEA ADC10 */
|
103 | #define USCIAB0TX_VECTOR 12 /* 0xFFEC USCI A0/B0 Transmit */
|
104 | #define USCIAB0RX_VECTOR 14 /* 0xFFEE USCI A0/B0 Receive */
|
105 | #define TIMERA1_VECTOR 16 /* 0xFFF0 Timer A CC1-2, TA */
|
106 | #define TIMERA0_VECTOR 18 /* 0xFFF2 Timer A CC0 */
|
107 | #define WDT_VECTOR 20 /* 0xFFF4 Watchdog Timer */
|
108 | #define TIMERB1_VECTOR 24 /* 0xFFF8 Timer B CC1-2, TB */
|
109 | #define TIMERB0_VECTOR 26 /* 0xFFFA Timer B CC0 */
|
110 |
|
111 | #define NMI_VECTOR 28 /* 0xFFFC Non-maskable */
|
112 |
|
113 | #define BSLSKEY_ 0xFFDE /* The address is used as bootstrap loader security key */
|
114 | #define BSLSKEY_DISABLE 0xAA55 /* Disables the BSL completely */
|
115 | #define BSLSKEY_NO_ERASE 0x0000 /* Disables the erasure of the flash if an invalid password is supplied */
|
116 |
|
117 | #endif /* #ifndef __msp430x22x4 */
|