1 | //******************************************************************************
|
2 | // MSP430x11x1 Demo - Timer_A, UART 19200 Echo, HF XTAL ACLK
|
3 | //
|
4 | // Description: Use Timer_A CCR0 hardware output modes and SCCI data latch to
|
5 | // to implement UART function @ 9600 baud. Software does not directly read and
|
6 | // write to RX and TX pins, instead proper use of output modes and SCCI data
|
7 | // latch are demonstrated. Use of these hardware features eliminates ISR
|
8 | // latency effects as hardware insures that output and input bit latching and
|
9 | // timing are perfectly synchronised with Timer_A regardless of other
|
10 | // software activity. In the Mainloop the UART function readies the UART to
|
11 | // receive one character and waits in LPM0 with all activity interrupt driven.
|
12 | // After a character has been received, the UART receive function forces exit
|
13 | // from LPM0 in the Mainloop which echo's back the received character.
|
14 | // ACLK = MCLK = TACLK = HF XTAL = 3.579545MHz
|
15 | // //* An external 3.579545Hz XTAL on XIN XOUT is required for ACLK *//
|
16 | //
|
17 | // MSP430F1121
|
18 | // -----------------
|
19 | // /|\| XIN|-
|
20 | // | | | 3.58Mhz
|
21 | // --|RST XOUT|-
|
22 | // | |
|
23 | // | CCI0A/TXD/P1.1|-------->
|
24 | // | | 19200 8N1
|
25 | // | CCI0B/RXD/P2.2|<--------
|
26 | //
|
27 | #define RXD 0x04 // RXD on P2.2
|
28 | #define TXD 0x02 // TXD on P1.1
|
29 |
|
30 |
|
31 | // Conditions for 19200 Baud HW/SW UART, ACLK = 3.579545MHz
|
32 |
|
33 | #define Bitime_5 83 // ~ 0.5 bit length
|
34 | #define Bitime 186 // ~ 19245 baud
|
35 |
|
36 |
|
37 |
|
38 | unsigned int RXTXData;
|
39 | unsigned char BitCnt;
|
40 |
|
41 | void TX_Byte (void);
|
42 | void RX_Ready (void);
|
43 | //
|
44 | // M. Buccini
|
45 | // Texas Instruments Inc.
|
46 | // Feb 2005
|
47 | // Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
|
48 | //*****************************************************************************
|
49 |
|
50 | #include <msp430x11x1.h>
|
51 |
|
52 |
|
53 | void main (void)
|
54 | {
|
55 | volatile unsigned int i;
|
56 | WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
|
57 |
|
58 | BCSCTL1 |= XTS; // ACLK = LFXT1 = HF XTAL
|
59 |
|
60 | do
|
61 | {
|
62 | IFG1 &= ~OFIFG; // Clear OSCFault flag
|
63 | for (i = 0xFF; i > 0; i--); // Time for flag to set
|
64 | }
|
65 | while ( IFG1 & OFIFG ); // OSCFault flag still set?
|
66 |
|
67 | BCSCTL2 |= SELM_3; // MCLK = LFXT1 (safe)
|
68 |
|
69 | CCTL0 = OUT; // TXD Idle as Mark
|
70 | TACTL = TASSEL_1 + MC_2; // ACLK, continuous mode
|
71 | P1SEL = TXD; // P1.1/TA0 for TXD function
|
72 | P1DIR = TXD; // TXD output on P1
|
73 | P2SEL = RXD; // P2.2/TA0 as RXD input
|
74 |
|
75 | // Mainloop
|
76 | for (;;)
|
77 | {
|
78 | RX_Ready(); // UART ready to RX one Byte
|
79 | _BIS_SR(CPUOFF + GIE); // Enter LPM0 w/ interr until char RXed
|
80 | TX_Byte(); // TX Back RXed Byte Received
|
81 | }
|
82 | }
|
83 |
|
84 |
|
85 | // Function Transmits Character from RXTXData Buffer
|
86 | void TX_Byte (void)
|
87 | {
|
88 | BitCnt = 0xA; // Load Bit counter, 8data + ST/SP
|
89 | CCR0 = TAR; // Current state of TA counter
|
90 | CCR0 += Bitime; // Some time till first bit
|
91 | RXTXData |= 0x100; // Add mark stop bit to RXTXData
|
92 | RXTXData = RXTXData << 1; // Add space start bit
|
93 | CCTL0 = OUTMOD0 + CCIE; // TXD = mark = idle
|
94 | while ( CCTL0 & CCIE ); // Wait for TX completion
|
95 | }
|
96 |
|
97 |
|
98 | // Function Readies UART to Receive Character into RXTXData Buffer
|
99 | void RX_Ready (void)
|
100 | {
|
101 | BitCnt = 0x8; // Load Bit counter
|
102 | CCTL0 = SCS + CCIS0 + OUTMOD0 + CM1 + CAP + CCIE; // Sync, Neg Edge, Capture
|
103 | }
|
104 |
|
105 |
|
106 | // Timer A0 interrupt service routine
|
107 | #pragma vector=TIMERA0_VECTOR
|
108 | __interrupt void Timer_A (void)
|
109 | {
|
110 | CCR0 += Bitime; // Add Offset to CCR0
|
111 |
|
112 | // RX
|
113 | if (CCTL0 & CCIS0) // RX on CCI0B?
|
114 | {
|
115 | if( CCTL0 & CAP ) // Capture mode = start bit edge
|
116 | {
|
117 | CCTL0 &= ~ CAP; // Switch from capture to compare mode
|
118 | CCR0 += Bitime_5;
|
119 | }
|
120 | else
|
121 | {
|
122 | RXTXData = RXTXData >> 1;
|
123 | if (CCTL0 & SCCI) // Get bit waiting in receive latch
|
124 | RXTXData |= 0x80;
|
125 | BitCnt --; // All bits RXed?
|
126 | if ( BitCnt == 0)
|
127 | //>>>>>>>>>> Decode of Received Byte Here <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
128 | {
|
129 | CCTL0 &= ~ CCIE; // All bits RXed, disable interrupt
|
130 | _BIC_SR_IRQ(CPUOFF); // Clear LPM0 bits from 0(SR)
|
131 | }
|
132 | //>>>>>>>>>> Decode of Received Byte Here <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
133 | }
|
134 | }
|
135 | // TX
|
136 | else
|
137 | {
|
138 | if ( BitCnt == 0)
|
139 | CCTL0 &= ~ CCIE; // All bits TXed, disable interrupt
|
140 | else
|
141 | {
|
142 | CCTL0 |= OUTMOD2; // TX Space
|
143 | if (RXTXData & 0x01)
|
144 | CCTL0 &= ~ OUTMOD2; // TX Mark
|
145 | RXTXData = RXTXData >> 1;
|
146 | BitCnt --;
|
147 | }
|
148 | }
|
149 | }
|