1 | // HEADER FILE
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2 | #if !defined ICD_DEBUG && !defined ICD2_DEBUG
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3 | #pragma chip PIC16F877A, core 14, code 8192, ram 32 : 0x1FF
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4 |
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5 | #elif defined ICD2_DEBUG
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6 | #pragma chip PIC16F877A, core 14, code 0x1F00, ram 32 : 0x1FF
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7 | // last 256 locations are reserved for debugging
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8 |
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9 | //RESERVED RAM LOCATIONS
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10 | char ICD2R1 @ 0x70;
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11 | char reservedICD2[11] @ 0x1E5; // reserved RAM for ICD2
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12 |
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13 | #pragma stackLevels 7 // reserve one level for debugging
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14 |
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15 | #else /* ICD_DEBUG */
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16 | #pragma chip PIC16F877A, core 14, code 0x1F00, ram 32 : 0x1FF
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17 | // NOTE: last 256 locations are reserved for debugging
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18 |
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19 | //RESERVED RAM LOCATIONS FOR DEBUGGING
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20 | #pragma char ICDR1 @ 0x70
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21 | #pragma char ICDR2 @ 0x1EB
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22 | #pragma char ICDR3 @ 0x1EC
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23 | #pragma char ICDR4 @ 0x1ED
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24 | #pragma char ICDR5 @ 0x1EE
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25 | #pragma char ICDR6 @ 0x1EF
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26 |
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27 | #pragma stackLevels 7 // reserve one level for debugging
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28 |
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29 | #pragma cdata[0] = /*NOP*/ 0x0000 // startup instruction
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30 | #pragma resetVector 1 // change to address 1
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31 |
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32 | #endif
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33 |
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34 | #pragma ramdef 0x110 : 0x11F
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35 | #pragma ramdef 0x190 : 0x19F
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36 | #pragma ramdef 0x70 : 0x7F mapped_into_all_banks
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37 |
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38 | #define INT_gen_style
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39 | #define INT_rambank 0 /* interrupt variables in bank 0 */
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40 |
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41 | #pragma config_def 0x1111
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42 |
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43 | #pragma wideConstData
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44 |
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45 | /* Predefined:
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46 | char W;
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47 | char INDF, TMR0, PCL, STATUS, FSR, PORTA, PORTB;
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48 | char OPTION, TRISA, TRISB;
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49 | char PCLATH, INTCON;
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50 | bit PS0, PS1, PS2, PSA, T0SE, T0CS, INTEDG, RBPU_;
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51 | bit Carry, DC, Zero_, PD, TO, RP0, RP1, IRP;
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52 | bit RBIF, INTF, T0IF, RBIE, INTE, T0IE, GIE;
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53 | bit PA0, PA1; // PCLATH
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54 | */
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55 |
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56 | #pragma char PORTC @ 7
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57 | #pragma char PORTD @ 8
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58 | #pragma char PORTE @ 9
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59 |
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60 | #pragma char PIR1 @ 12
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61 | #pragma char PIR2 @ 13
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62 | #pragma char TMR1L @ 14
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63 | #pragma char TMR1H @ 15
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64 | #pragma char T1CON @ 16
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65 | #pragma char TMR2 @ 17
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66 | #pragma char T2CON @ 18
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67 | #pragma char SSPBUF @ 19
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68 | #pragma char SSPCON @ 20
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69 | #pragma char CCPR1L @ 21
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70 | #pragma char CCPR1H @ 22
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71 | #pragma char CCP1CON @ 23
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72 | #pragma char RCSTA @ 24
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73 | #pragma char TXREG @ 25
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74 | #pragma char RCREG @ 26
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75 | #pragma char CCPR2L @ 27
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76 | #pragma char CCPR2H @ 28
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77 | #pragma char CCP2CON @ 29
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78 | #pragma char ADRESH @ 30
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79 | #pragma char ADCON0 @ 31
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80 |
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81 | #pragma char TRISC @ 0x87
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82 | #pragma char TRISD @ 0x88
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83 | #pragma char TRISE @ 0x89
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84 |
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85 | #pragma char PIE1 @ 0x8C
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86 | #pragma char PIE2 @ 0x8D
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87 | #pragma char PCON @ 0x8E
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88 |
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89 | #pragma char SSPCON2 @ 0x91
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90 | #pragma char PR2 @ 0x92
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91 | #pragma char SSPADD @ 0x93
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92 | #pragma char SSPSTAT @ 0x94
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93 |
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94 | #pragma char TXSTA @ 0x98
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95 | #pragma char SPBRG @ 0x99
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96 |
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97 | #pragma char CMCON @ 0x9C
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98 | #pragma char CVRCON @ 0x9D
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99 | #pragma char ADRESL @ 0x9E
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100 | #pragma char ADCON1 @ 0x9F
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101 |
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102 | #pragma char EEDATA @ 0x10C
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103 | #pragma char EEADR @ 0x10D
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104 | #pragma char EEDATH @ 0x10E
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105 | #pragma char EEADRH @ 0x10F
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106 |
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107 | #pragma char EECON1 @ 0x18C
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108 | #pragma char EECON2 @ 0x18D
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109 |
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110 |
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111 | #pragma bit PEIE @ 11.6 mapped_into_all_banks
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112 |
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113 | #pragma bit TMR1IF @ 12.0
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114 | #pragma bit TMR2IF @ 12.1
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115 | #pragma bit CCP1IF @ 12.2
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116 | #pragma bit SSPIF @ 12.3
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117 | #pragma bit TXIF @ 12.4
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118 | #pragma bit RCIF @ 12.5
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119 | #pragma bit ADIF @ 12.6
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120 | #pragma bit PSPIF @ 12.7
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121 |
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122 | #pragma bit CCP2IF @ 13.0
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123 | #pragma bit BCLIF @ 13.3
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124 | #pragma bit EEIF @ 13.4
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125 | #pragma bit CMIF @ 13.6
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126 |
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127 | #pragma bit TMR1ON @ 16.0
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128 | #pragma bit TMR1CS @ 16.1
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129 | #pragma bit T1SYNC_ @ 16.2
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130 | #pragma bit T1OSCEN @ 16.3
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131 | #pragma bit T1CKPS0 @ 16.4
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132 | #pragma bit T1CKPS1 @ 16.5
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133 |
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134 | #pragma bit T2CKPS0 @ 18.0
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135 | #pragma bit T2CKPS1 @ 18.1
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136 | #pragma bit TMR2ON @ 18.2
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137 | #pragma bit TOUTPS0 @ 18.3
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138 | #pragma bit TOUTPS1 @ 18.4
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139 | #pragma bit TOUTPS2 @ 18.5
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140 | #pragma bit TOUTPS3 @ 18.6
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141 |
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142 | #pragma bit SSPM0 @ 20.0
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143 | #pragma bit SSPM1 @ 20.1
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144 | #pragma bit SSPM2 @ 20.2
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145 | #pragma bit SSPM3 @ 20.3
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146 | #pragma bit CKP @ 20.4
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147 | #pragma bit SSPEN @ 20.5
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148 | #pragma bit SSPOV @ 20.6
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149 | #pragma bit WCOL @ 20.7
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150 |
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151 | #pragma bit CCP1M0 @ 23.0
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152 | #pragma bit CCP1M1 @ 23.1
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153 | #pragma bit CCP1M2 @ 23.2
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154 | #pragma bit CCP1M3 @ 23.3
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155 | #pragma bit CCP1Y @ 23.4
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156 | #pragma bit CCP1X @ 23.5
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157 |
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158 | #pragma bit RX9D @ 24.0
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159 | #pragma bit OERR @ 24.1
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160 | #pragma bit FERR @ 24.2
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161 | #pragma bit ADDEN @ 24.3
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162 | #pragma bit CREN @ 24.4
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163 | #pragma bit SREN @ 24.5
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164 | #pragma bit RX9 @ 24.6
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165 | #pragma bit SPEN @ 24.7
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166 |
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167 | #pragma bit CCP2M0 @ 29.0
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168 | #pragma bit CCP2M1 @ 29.1
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169 | #pragma bit CCP2M2 @ 29.2
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170 | #pragma bit CCP2M3 @ 29.3
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171 | #pragma bit CCP2Y @ 29.4
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172 | #pragma bit CCP2X @ 29.5
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173 |
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174 | #pragma bit ADON @ 31.0
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175 | #pragma bit GO @ 31.2
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176 | #pragma bit CHS0 @ 31.3
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177 | #pragma bit CHS1 @ 31.4
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178 | #pragma bit CHS2 @ 31.5
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179 | #pragma bit ADCS0 @ 31.6
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180 | #pragma bit ADCS1 @ 31.7
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181 |
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182 | #pragma bit PSPMODE @ 0x89.4
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183 | #pragma bit IBOV @ 0x89.5
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184 | #pragma bit OBF @ 0x89.6
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185 | #pragma bit IBF @ 0x89.7
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186 |
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187 | #pragma bit TMR1IE @ 0x8C.0
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188 | #pragma bit TMR2IE @ 0x8C.1
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189 | #pragma bit CCP1IE @ 0x8C.2
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190 | #pragma bit SSPIE @ 0x8C.3
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191 | #pragma bit TXIE @ 0x8C.4
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192 | #pragma bit RCIE @ 0x8C.5
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193 | #pragma bit ADIE @ 0x8C.6
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194 | #pragma bit PSPIE @ 0x8C.7
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195 |
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196 | #pragma bit CCP2IE @ 0x8D.0
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197 | #pragma bit BCLIE @ 0x8D.3
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198 | #pragma bit EEIE @ 0x8D.4
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199 | #pragma bit CMIE @ 0x8D.6
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200 |
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201 | #pragma bit BOR_ @ 0x8E.0
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202 | #pragma bit POR_ @ 0x8E.1
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203 |
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204 | #pragma bit SEN @ 0x91.0
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205 | #pragma bit RSEN @ 0x91.1
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206 | #pragma bit PEN @ 0x91.2
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207 | #pragma bit RCEN @ 0x91.3
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208 | #pragma bit ACKEN @ 0x91.4
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209 | #pragma bit ACKDT @ 0x91.5
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210 | #pragma bit ACKSTAT @ 0x91.6
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211 | #pragma bit GCEN @ 0x91.7
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212 |
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213 | #pragma bit BF @ 0x94.0
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214 | #pragma bit UA @ 0x94.1
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215 | #pragma bit RW_ @ 0x94.2
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216 | #pragma bit S @ 0x94.3
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217 | #pragma bit P @ 0x94.4
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218 | #pragma bit DA_ @ 0x94.5
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219 | #pragma bit CKE @ 0x94.6
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220 | #pragma bit SMP @ 0x94.7
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221 |
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222 | #pragma bit TX9D @ 0x98.0
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223 | #pragma bit TRMT @ 0x98.1
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224 | #pragma bit BRGH @ 0x98.2
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225 | #pragma bit SYNC @ 0x98.4
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226 | #pragma bit TXEN @ 0x98.5
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227 | #pragma bit TX9 @ 0x98.6
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228 | #pragma bit CSRC @ 0x98.7
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229 |
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230 | #pragma bit CM0 @ 0x9C.0
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231 | #pragma bit CM1 @ 0x9C.1
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232 | #pragma bit CM2 @ 0x9C.2
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233 | #pragma bit CIS @ 0x9C.3
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234 | #pragma bit C1INV @ 0x9C.4
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235 | #pragma bit C2INV @ 0x9C.5
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236 | #pragma bit C1OUT @ 0x9C.6
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237 | #pragma bit C2OUT @ 0x9C.7
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238 |
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239 | #pragma bit CVR0 @ 0x9D.0
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240 | #pragma bit CVR1 @ 0x9D.1
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241 | #pragma bit CVR2 @ 0x9D.2
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242 | #pragma bit CVR3 @ 0x9D.3
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243 | #pragma bit CVRR @ 0x9D.5
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244 | #pragma bit CVROE @ 0x9D.6
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245 | #pragma bit CVREN @ 0x9D.7
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246 |
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247 | #pragma bit PCFG0 @ 0x9F.0
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248 | #pragma bit PCFG1 @ 0x9F.1
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249 | #pragma bit PCFG2 @ 0x9F.2
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250 | #pragma bit PCFG3 @ 0x9F.3
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251 | #pragma bit ADCS2 @ 0x9F.6
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252 | #pragma bit ADFM @ 0x9F.7
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253 |
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254 | #pragma bit RD @ 0x18C.0
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255 | #pragma bit WR @ 0x18C.1
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256 | #pragma bit WREN @ 0x18C.2
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257 | #pragma bit WRERR @ 0x18C.3
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258 | #pragma bit EEPGD @ 0x18C.7
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