1 | ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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2 | ;***** Created: 2011-02-09 12:03 ******* Source: ATtiny13A.xml ***********
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3 | ;*************************************************************************
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4 | ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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5 | ;*
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6 | ;* Number : AVR000
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7 | ;* File Name : "tn13Adef.inc"
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8 | ;* Title : Register/Bit Definitions for the ATtiny13A
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9 | ;* Date : 2011-02-09
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10 | ;* Version : 2.35
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11 | ;* Support E-mail : avr@atmel.com
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12 | ;* Target MCU : ATtiny13A
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13 | ;*
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14 | ;* DESCRIPTION
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15 | ;* When including this file in the assembly program file, all I/O register
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16 | ;* names and I/O register bit names appearing in the data book can be used.
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17 | ;* In addition, the six registers forming the three data pointers X, Y and
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18 | ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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19 | ;* SRAM is also defined
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20 | ;*
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21 | ;* The Register names are represented by their hexadecimal address.
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22 | ;*
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23 | ;* The Register Bit names are represented by their bit number (0-7).
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24 | ;*
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25 | ;* Please observe the difference in using the bit names with instructions
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26 | ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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27 | ;* (skip if bit in register set/cleared). The following example illustrates
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28 | ;* this:
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29 | ;*
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30 | ;* in r16,PORTB ;read PORTB latch
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31 | ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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32 | ;* out PORTB,r16 ;output to PORTB
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33 | ;*
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34 | ;* in r16,TIFR ;read the Timer Interrupt Flag Register
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35 | ;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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36 | ;* rjmp TOV0_is_set ;jump if set
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37 | ;* ... ;otherwise do something else
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38 | ;*************************************************************************
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39 |
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40 | ifndef _TN13ADEF_INC_
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41 | #define _TN13ADEF_INC_
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42 |
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43 |
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44 | ; #pragma partinc 0
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45 |
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46 | ; ***** SPECIFY DEVICE ***************************************************
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47 | cpu atmega8 ;.device ATtiny13A
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48 | ; #pragma AVRPART ADMIN PART_NAME ATtiny13A
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49 | SIGNATURE_000: equ 0x1e
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50 | SIGNATURE_001: equ 0x90
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51 | SIGNATURE_002: equ 0x07
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52 |
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53 | ; #pragma AVRPART CORE CORE_VERSION V2
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54 | ; #pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
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55 |
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56 |
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57 | ; ***** I/O REGISTER DEFINITIONS *****************************************
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58 | ; NOTE:
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59 | ; Definitions marked "MEMORY MAPPED"are extended I/O ports
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60 | ; and cannot be used with IN/OUT instructions
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61 | SREG: equ 0x3f
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62 | SPL: equ 0x3d
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63 | GIMSK: equ 0x3b
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64 | GIFR: equ 0x3a
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65 | TIMSK0: equ 0x39
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66 | TIFR0: equ 0x38
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67 | SPMCSR: equ 0x37
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68 | OCR0A: equ 0x36
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69 | MCUCR: equ 0x35
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70 | MCUSR: equ 0x34
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71 | TCCR0B: equ 0x33
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72 | TCNT0: equ 0x32
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73 | OSCCAL: equ 0x31
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74 | BODCR: equ 0x30
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75 | TCCR0A: equ 0x2f
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76 | DWDR: equ 0x2e
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77 | OCR0B: equ 0x29
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78 | GTCCR: equ 0x28
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79 | CLKPR: equ 0x26
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80 | PRR: equ 0x25
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81 | WDTCR: equ 0x21
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82 | EEAR: equ 0x1e
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83 | EEDR: equ 0x1d
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84 | EECR: equ 0x1c
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85 | PORTB: equ 0x18
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86 | DDRB: equ 0x17
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87 | PINB: equ 0x16
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88 | PCMSK: equ 0x15
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89 | DIDR0: equ 0x14
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90 | ACSR: equ 0x08
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91 | ADMUX: equ 0x07
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92 | ADCSRA: equ 0x06
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93 | ADCH: equ 0x05
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94 | ADCL: equ 0x04
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95 | ADCSRB: equ 0x03
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96 |
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97 |
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98 | ; ***** BIT DEFINITIONS **************************************************
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99 |
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100 | ; ***** AD_CONVERTER *****************
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101 | ; ADMUX - The ADC multiplexer Selection Register
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102 | MUX0: equ 0 ; Analog Channel and Gain Selection Bits
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103 | MUX1: equ 1 ; Analog Channel and Gain Selection Bits
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104 | ADLAR: equ 5 ; Left Adjust Result
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105 | REFS0: equ 6 ; Reference Selection Bit 0
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106 |
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107 | ; ADCSRA - The ADC Control and Status register
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108 | ADPS0: equ 0 ; ADC Prescaler Select Bits
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109 | ADPS1: equ 1 ; ADC Prescaler Select Bits
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110 | ADPS2: equ 2 ; ADC Prescaler Select Bits
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111 | ADIE: equ 3 ; ADC Interrupt Enable
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112 | ADIF: equ 4 ; ADC Interrupt Flag
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113 | ADATE: equ 5 ; ADC Auto Trigger Enable
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114 | ADSC: equ 6 ; ADC Start Conversion
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115 | ADEN: equ 7 ; ADC Enable
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116 |
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117 | ; ADCH - ADC Data Register High Byte
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118 | ADCH0: equ 0 ; ADC Data Register High Byte Bit 0
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119 | ADCH1: equ 1 ; ADC Data Register High Byte Bit 1
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120 | ADCH2: equ 2 ; ADC Data Register High Byte Bit 2
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121 | ADCH3: equ 3 ; ADC Data Register High Byte Bit 3
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122 | ADCH4: equ 4 ; ADC Data Register High Byte Bit 4
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123 | ADCH5: equ 5 ; ADC Data Register High Byte Bit 5
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124 | ADCH6: equ 6 ; ADC Data Register High Byte Bit 6
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125 | ADCH7: equ 7 ; ADC Data Register High Byte Bit 7
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126 |
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127 | ; ADCL - ADC Data Register Low Byte
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128 | ADCL0: equ 0 ; ADC Data Register Low Byte Bit 0
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129 | ADCL1: equ 1 ; ADC Data Register Low Byte Bit 1
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130 | ADCL2: equ 2 ; ADC Data Register Low Byte Bit 2
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131 | ADCL3: equ 3 ; ADC Data Register Low Byte Bit 3
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132 | ADCL4: equ 4 ; ADC Data Register Low Byte Bit 4
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133 | ADCL5: equ 5 ; ADC Data Register Low Byte Bit 5
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134 | ADCL6: equ 6 ; ADC Data Register Low Byte Bit 6
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135 | ADCL7: equ 7 ; ADC Data Register Low Byte Bit 7
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136 |
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137 | ; ADCSRB - ADC Control and Status Register B
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138 | ADTS0: equ 0 ; ADC Auto Trigger Source 0
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139 | ADTS1: equ 1 ; ADC Auto Trigger Source 1
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140 | ADTS2: equ 2 ; ADC Auto Trigger Source 2
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141 |
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142 | ; DIDR0 - Digital Input Disable Register 0
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143 | ADC1D: equ 2 ; ADC2 Digital input Disable
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144 | ADC3D: equ 3 ; ADC3 Digital input Disable
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145 | ADC2D: equ 4 ; ADC2 Digital input Disable
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146 | ADC0D: equ 5 ; ADC0 Digital input Disable
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147 |
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148 |
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149 | ; ***** ANALOG_COMPARATOR ************
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150 | ; ADCSRB - ADC Control and Status Register B
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151 | ACME: equ 6 ; Analog Comparator Multiplexer Enable
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152 |
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153 | ; ACSR - Analog Comparator Control And Status Register
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154 | ACIS0: equ 0 ; Analog Comparator Interrupt Mode Select bit 0
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155 | ACIS1: equ 1 ; Analog Comparator Interrupt Mode Select bit 1
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156 | ACIE: equ 3 ; Analog Comparator Interrupt Enable
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157 | ACI: equ 4 ; Analog Comparator Interrupt Flag
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158 | ACO: equ 5 ; Analog Compare Output
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159 | ACBG: equ 6 ; Analog Comparator Bandgap Select
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160 | AINBG: equ ACBG ; For compatibility
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161 | ACD: equ 7 ; Analog Comparator Disable
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162 |
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163 | ; DIDR0 -
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164 | AIN0D: equ 0 ; AIN0 Digital Input Disable
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165 | AIN1D: equ 1 ; AIN1 Digital Input Disable
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166 |
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167 |
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168 | ; ***** EEPROM ***********************
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169 | ; EEAR - EEPROM Read/Write Access
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170 | EEARL: equ EEAR ; For compatibility
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171 | EEAR0: equ 0 ; EEPROM Read/Write Access bit 0
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172 | EEAR1: equ 1 ; EEPROM Read/Write Access bit 1
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173 | EEAR2: equ 2 ; EEPROM Read/Write Access bit 2
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174 | EEAR3: equ 3 ; EEPROM Read/Write Access bit 3
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175 | EEAR4: equ 4 ; EEPROM Read/Write Access bit 4
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176 | EEAR5: equ 5 ; EEPROM Read/Write Access bit 5
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177 |
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178 | ; EEDR - EEPROM Data Register
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179 | EEDR0: equ 0 ; EEPROM Data Register bit 0
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180 | EEDR1: equ 1 ; EEPROM Data Register bit 1
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181 | EEDR2: equ 2 ; EEPROM Data Register bit 2
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182 | EEDR3: equ 3 ; EEPROM Data Register bit 3
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183 | EEDR4: equ 4 ; EEPROM Data Register bit 4
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184 | EEDR5: equ 5 ; EEPROM Data Register bit 5
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185 | EEDR6: equ 6 ; EEPROM Data Register bit 6
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186 | EEDR7: equ 7 ; EEPROM Data Register bit 7
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187 |
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188 | ; EECR - EEPROM Control Register
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189 | EERE: equ 0 ; EEPROM Read Enable
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190 | EEWE: equ 1 ; EEPROM Write Enable
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191 | EEPE: equ EEWE ; For compatibility
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192 | EEMWE: equ 2 ; EEPROM Master Write Enable
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193 | EEMPE: equ EEMWE ; For compatibility
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194 | EERIE: equ 3 ; EEProm Ready Interrupt Enable
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195 | EEPM0: equ 4 ;
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196 | EEPM1: equ 5 ;
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197 |
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198 |
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199 | ; ***** PORTB ************************
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200 | ; PORTB - Data Register, Port B
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201 | PORTB0: equ 0 ;
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202 | PB0: equ 0 ; For compatibility
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203 | PORTB1: equ 1 ;
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204 | PB1: equ 1 ; For compatibility
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205 | PORTB2: equ 2 ;
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206 | PB2: equ 2 ; For compatibility
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207 | PORTB3: equ 3 ;
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208 | PB3: equ 3 ; For compatibility
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209 | PORTB4: equ 4 ;
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210 | PB4: equ 4 ; For compatibility
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211 | PORTB5: equ 5 ;
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212 | PB5: equ 5 ; For compatibility
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213 |
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214 | ; DDRB - Data Direction Register, Port B
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215 | DDB0: equ 0 ;
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216 | DDB1: equ 1 ;
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217 | DDB2: equ 2 ;
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218 | DDB3: equ 3 ;
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219 | DDB4: equ 4 ;
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220 | DDB5: equ 5 ;
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221 |
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222 | ; PINB - Input Pins, Port B
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223 | PINB0: equ 0 ;
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224 | PINB1: equ 1 ;
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225 | PINB2: equ 2 ;
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226 | PINB3: equ 3 ;
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227 | PINB4: equ 4 ;
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228 | PINB5: equ 5 ;
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229 |
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230 |
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231 | ; ***** EXTERNAL_INTERRUPT ***********
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232 | ; MCUCR - MCU Control Register
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233 | ISC00: equ 0 ; Interrupt Sense Control 0 Bit 0
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234 | ISC01: equ 1 ; Interrupt Sense Control 0 Bit 1
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235 |
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236 | ; GIMSK - General Interrupt Mask Register
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237 | GICR: equ GIMSK ; For compatibility
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238 | PCIE: equ 5 ; Pin Change Interrupt Enable
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239 | INT0: equ 6 ; External Interrupt Request 0 Enable
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240 |
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241 | ; GIFR - General Interrupt Flag register
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242 | PCIF: equ 5 ; Pin Change Interrupt Flag
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243 | INTF0: equ 6 ; External Interrupt Flag 0
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244 |
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245 | ; PCMSK - Pin Change Enable Mask
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246 | PCINT0: equ 0 ; Pin Change Enable Mask Bit 0
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247 | PCINT1: equ 1 ; Pin Change Enable Mask Bit 1
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248 | PCINT2: equ 2 ; Pin Change Enable Mask Bit 2
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249 | PCINT3: equ 3 ; Pin Change Enable Mask Bit 3
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250 | PCINT4: equ 4 ; Pin Change Enable Mask Bit 4
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251 | PCINT5: equ 5 ; Pin Change Enable Mask Bit 5
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252 |
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253 |
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254 | ; ***** TIMER_COUNTER_0 **************
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255 | ; TIMSK0 - Timer/Counter0 Interrupt Mask Register
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256 | TOIE0: equ 1 ; Timer/Counter0 Overflow Interrupt Enable
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257 | OCIE0A: equ 2 ; Timer/Counter0 Output Compare Match A Interrupt Enable
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258 | OCIE0B: equ 3 ; Timer/Counter0 Output Compare Match B Interrupt Enable
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259 |
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260 | ; TIFR0 - Timer/Counter0 Interrupt Flag register
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261 | TOV0: equ 1 ; Timer/Counter0 Overflow Flag
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262 | OCF0A: equ 2 ; Timer/Counter0 Output Compare Flag 0A
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263 | OCF0B: equ 3 ; Timer/Counter0 Output Compare Flag 0B
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264 |
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265 | ; OCR0A - Timer/Counter0 Output Compare Register
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266 | OCR0A_0: equ 0 ;
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267 | OCR0A_1: equ 1 ;
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268 | OCR0A_2: equ 2 ;
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269 | OCR0A_3: equ 3 ;
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270 | OCR0A_4: equ 4 ;
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271 | OCR0A_5: equ 5 ;
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272 | OCR0A_6: equ 6 ;
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273 | OCR0A_7: equ 7 ;
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274 |
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275 | ; TCCR0A - Timer/Counter Control Register A
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276 | WGM00: equ 0 ; Waveform Generation Mode
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277 | WGM01: equ 1 ; Waveform Generation Mode
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278 | COM0B0: equ 4 ; Compare Match Output B Mode
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279 | COM0B1: equ 5 ; Compare Match Output B Mode
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280 | COM0A0: equ 6 ; Compare Match Output A Mode
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281 | COM0A1: equ 7 ; Compare Match Output A Mode
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282 |
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283 | ; TCNT0 - Timer/Counter0
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284 | TCNT0_0: equ 0 ;
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285 | TCNT0_1: equ 1 ;
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286 | TCNT0_2: equ 2 ;
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287 | TCNT0_3: equ 3 ;
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288 | TCNT0_4: equ 4 ;
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289 | TCNT0_5: equ 5 ;
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290 | TCNT0_6: equ 6 ;
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291 | TCNT0_7: equ 7 ;
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292 |
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293 | ; TCCR0B - Timer/Counter Control Register B
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294 | CS00: equ 0 ; Clock Select
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295 | CS01: equ 1 ; Clock Select
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296 | CS02: equ 2 ; Clock Select
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297 | WGM02: equ 3 ; Waveform Generation Mode
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298 | FOC0B: equ 6 ; Force Output Compare B
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299 | FOC0A: equ 7 ; Force Output Compare A
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300 |
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301 | ; OCR0B - Timer/Counter0 Output Compare Register
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302 | OCR0B_0: equ 0 ;
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303 | OCR0B_1: equ 1 ;
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304 | OCR0B_2: equ 2 ;
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305 | OCR0B_3: equ 3 ;
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306 | OCR0B_4: equ 4 ;
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307 | OCR0B_5: equ 5 ;
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308 | OCR0B_6: equ 6 ;
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309 | OCR0B_7: equ 7 ;
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310 |
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311 | ; GTCCR - General Timer Conuter Register
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312 | PSR10: equ 0 ; Prescaler Reset Timer/Counter0
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313 | TSM: equ 7 ; Timer/Counter Synchronization Mode
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314 |
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315 |
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316 | ; ***** WATCHDOG *********************
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317 | ; WDTCR - Watchdog Timer Control Register
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318 | WDP0: equ 0 ; Watch Dog Timer Prescaler bit 0
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319 | WDP1: equ 1 ; Watch Dog Timer Prescaler bit 1
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320 | WDP2: equ 2 ; Watch Dog Timer Prescaler bit 2
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321 | WDE: equ 3 ; Watch Dog Enable
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322 | WDCE: equ 4 ; Watchdog Change Enable
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323 | WDP3: equ 5 ; Watchdog Timer Prescaler Bit 3
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324 | WDTIE: equ 6 ; Watchdog Timeout Interrupt Enable
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325 | WDTIF: equ 7 ; Watchdog Timeout Interrupt Flag
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326 |
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327 |
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328 | ; ***** CPU **************************
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329 | ; SREG - Status Register
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330 | SREG_C: equ 0 ; Carry Flag
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331 | SREG_Z: equ 1 ; Zero Flag
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332 | SREG_N: equ 2 ; Negative Flag
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333 | SREG_V: equ 3 ; Two's Complement Overflow Flag
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334 | SREG_S: equ 4 ; Sign Bit
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335 | SREG_H: equ 5 ; Half Carry Flag
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336 | SREG_T: equ 6 ; Bit Copy Storage
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337 | SREG_I: equ 7 ; Global Interrupt Enable
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338 |
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339 | ; SPL - Stack Pointer Low Byte
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340 | SP0: equ 0 ; Stack Pointer Bit 0
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341 | SP1: equ 1 ; Stack Pointer Bit 1
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342 | SP2: equ 2 ; Stack Pointer Bit 2
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343 | SP3: equ 3 ; Stack Pointer Bit 3
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344 | SP4: equ 4 ; Stack Pointer Bit 4
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345 | SP5: equ 5 ; Stack Pointer Bit 5
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346 | SP6: equ 6 ; Stack Pointer Bit 6
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347 | SP7: equ 7 ; Stack Pointer Bit 7
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348 |
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349 | ; MCUCR - MCU Control Register
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350 | ;.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
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351 | ;.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
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352 | SM0: equ 3 ; Sleep Mode Select Bit 0
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353 | SM1: equ 4 ; Sleep Mode Select Bit 1
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354 | SE: equ 5 ; Sleep Enable
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355 | PUD: equ 6 ; Pull-up Disable
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356 |
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357 | ; MCUSR - MCU Status register
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358 | PORF: equ 0 ; Power-On Reset Flag
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359 | EXTRF: equ 1 ; External Reset Flag
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360 | BORF: equ 2 ; Brown-out Reset Flag
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361 | WDRF: equ 3 ; Watchdog Reset Flag
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362 |
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363 | ; OSCCAL - Oscillator Calibration Register
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364 | CAL0: equ 0 ; Oscillatro Calibration Value Bit 0
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365 | CAL1: equ 1 ; Oscillatro Calibration Value Bit 1
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366 | CAL2: equ 2 ; Oscillatro Calibration Value Bit 2
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367 | CAL3: equ 3 ; Oscillatro Calibration Value Bit 3
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368 | CAL4: equ 4 ; Oscillatro Calibration Value Bit 4
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369 | CAL5: equ 5 ; Oscillatro Calibration Value Bit 5
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370 | CAL6: equ 6 ; Oscillatro Calibration Value Bit 6
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371 |
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372 | ; CLKPR - Clock Prescale Register
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373 | CLKPS0: equ 0 ; Clock Prescaler Select Bit 0
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374 | CLKPS1: equ 1 ; Clock Prescaler Select Bit 1
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375 | CLKPS2: equ 2 ; Clock Prescaler Select Bit 2
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376 | CLKPS3: equ 3 ; Clock Prescaler Select Bit 3
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377 | CLKPCE: equ 7 ; Clock Prescaler Change Enable
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378 |
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379 | ; DWDR - Debug Wire Data Register
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380 | DWDR0: equ 0 ; Debug Wire Data Register Bit 0
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381 | DWDR1: equ 1 ; Debug Wire Data Register Bit 1
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382 | DWDR2: equ 2 ; Debug Wire Data Register Bit 2
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383 | DWDR3: equ 3 ; Debug Wire Data Register Bit 3
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384 | DWDR4: equ 4 ; Debug Wire Data Register Bit 4
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385 | DWDR5: equ 5 ; Debug Wire Data Register Bit 5
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386 | DWDR6: equ 6 ; Debug Wire Data Register Bit 6
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387 | DWDR7: equ 7 ; Debug Wire Data Register Bit 7
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388 |
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389 | ; SPMCSR - Store Program Memory Control and Status Register
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390 | SPMEN: equ 0 ; Store program Memory Enable
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391 | PGERS: equ 1 ; Page Erase
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392 | PGWRT: equ 2 ; Page Write
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393 | RFLB: equ 3 ; Read Fuse and Lock Bits
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394 | CTPB: equ 4 ; Clear Temporary Page Buffer
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395 |
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396 | ; PRR - Power Reduction Register
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397 | PRADC: equ 0 ; Power Reduction ADC
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398 | PRTIM0: equ 1 ; Power Reduction Timer/Counter0
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399 |
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400 | ; BODCR - BOD Control Register
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401 | BPDSE: equ 0 ; BOD Power-Down Sleep Enable
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402 | BPDS: equ 1 ; BOD Power-Down in Power-Down Sleep
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403 |
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404 |
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405 |
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406 | ; ***** LOCKSBITS ********************************************************
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407 | LB1: equ 0 ; Lockbit
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408 | LB2: equ 1 ; Lockbit
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409 |
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410 |
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411 | ; ***** FUSES ************************************************************
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412 | ; LOW fuse bits
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413 | CKSEL0: equ 0 ; Select Clock Source
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414 | CKSEL1: equ 1 ; Select Clock Source
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415 | SUT0: equ 2 ; Select start-up time
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416 | SUT1: equ 3 ; Select start-up time
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417 | CKDIV8: equ 4 ; Start up with system clock divided by 8
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418 | WDTON: equ 5 ; Watch dog timer always on
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419 | EESAVE: equ 6 ; Keep EEprom contents during chip erase
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420 | SPIEN: equ 7 ; SPI programming enable
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421 |
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422 | ; HIGH fuse bits
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423 | RSTDISBL: equ 0 ; Disable external reset
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424 | BODLEVEL0: equ 1 ; Enable BOD and select level
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425 | BODLEVEL1: equ 2 ; Enable BOD and select level
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426 | DWEN: equ 3 ; DebugWire Enable
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427 | SELFPRGEN: equ 4 ; Self Programming Enable
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428 |
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429 |
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430 |
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431 | ; ***** CPU REGISTER DEFINITIONS *****************************************
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432 | XH: reg r27
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433 | XL: reg r26
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434 | YH: reg r29
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435 | YL: reg r28
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436 | ZH: reg r31
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437 | ZL: reg r30
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438 |
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439 |
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440 |
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441 | ; ***** DATA MEMORY DECLARATIONS *****************************************
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442 | FLASHEND: equ 0x01ff ; Note: Word address
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443 | IOEND: equ 0x003f
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444 | SRAM_START: equ 0x0060
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445 | SRAM_SIZE: equ 64
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446 | RAMEND: equ 0x009f
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447 | XRAMEND: equ 0x0000
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448 | E2END: equ 0x003f
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449 | EEPROMEND: equ 0x003f
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450 | EEADRBITS: equ 6
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451 | ; #pragma AVRPART MEMORY PROG_FLASH 1024
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452 | ; #pragma AVRPART MEMORY EEPROM 64
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453 | ; #pragma AVRPART MEMORY INT_SRAM SIZE 64
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454 | ; #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
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455 |
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456 |
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457 |
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458 | ; ***** BOOTLOADER DECLARATIONS ******************************************
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459 | PAGESIZE: equ 16
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460 |
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461 |
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462 |
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463 | ; ***** INTERRUPT VECTORS ************************************************
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464 | INT0addr: equ 0x0001 ; External Interrupt 0
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465 | PCI0addr: equ 0x0002 ; External Interrupt Request 0
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466 | OVF0addr: equ 0x0003 ; Timer/Counter0 Overflow
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467 | ERDYaddr: equ 0x0004 ; EEPROM Ready
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468 | ACIaddr: equ 0x0005 ; Analog Comparator
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469 | OC0Aaddr: equ 0x0006 ; Timer/Counter Compare Match A
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470 | OC0Baddr: equ 0x0007 ; Timer/Counter Compare Match B
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471 | WDTaddr: equ 0x0008 ; Watchdog Time-out
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472 | ADCCaddr: equ 0x0009 ; ADC Conversion Complete
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473 |
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474 | INT_VECTORS_SIZE: equ 10 ; size in words
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475 |
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476 | endif; /* _TN13ADEF_INC_ */
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477 |
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478 | ; ***** END OF FILE ******************************************************
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