LVDS_CLOCK_IN.vhd

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-- Company: 

-- Engineer: 

-- 

-- Create Date:    11:59:57 10/12/2009 

-- Design Name: 

-- Module Name:    LVDS_CLOCK_IN - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

Library UNISIM;

use UNISIM.vcomponents.all;

entity LVDS_CLOCK_IN is

   Port (  AFE_CLK_P : in  STD_LOGIC;

          AFE_CLK_N : in  STD_LOGIC;

--        AFE_DAT_P : in  STD_LOGIC;

--         AFE_DAT_N : in  STD_LOGIC;

        DCM_RESET : in STD_LOGIC;

--        DDR_RESET : in STD_LOGIC;

--        SET_DDR : in STD_LOGIC;

        CLOCK_OUT0 : out STD_LOGIC;

        CLOCK_OUT180 : out STD_LOGIC

--        DATA_OUTQ0 : out STD_LOGIC;

--        DATA_OUTQ1 : out STD_LOGIC

      );

end LVDS_CLOCK_IN;

architecture Behavioral of LVDS_CLOCK_IN is

signal CLOCK_INT : STD_LOGIC;

signal CLOCK_OUT0_int : STD_LOGIC;

signal CLOCK_OUT180_int : STD_LOGIC;

--signal CLOCK_OUT0_out : STD_LOGIC;

--signal CLOCK_OUT180_out : STD_LOGIC;

signal CLKFB_in : STD_LOGIC;

--signal DATA_INT : STD_LOGIC;

--constant IDDR2_CE : STD_LOGIC := '1';

begin

A : IBUFGDS

      port map (O => CLOCK_INT,

                I => AFE_CLK_P,

                IB => AFE_CLK_N);

--B : IBUFDS

--      port map (O => DATA_INT,

--                I => AFE_DAT_P,

--                IB => AFE_DAT_N);

C : BUFG

      port map (I=>CLOCK_OUT0_int,

                O=>CLOCK_OUT0);

D : BUFG

      port map (I=>CLOCK_OUT0_int,

                O=>CLKFB_in);

D1 : BUFG

      port map (I=>CLOCK_OUT180_int,

                O=>CLOCK_OUT180);

E : DCM_SP

   generic map (

      CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5

                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0

      CLKFX_DIVIDE => 2,   --  Can be any interger from 1 to 32

      CLKFX_MULTIPLY => 2, --  Can be any integer from 1 to 32

      CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature

      CLKIN_PERIOD => 6.25, --  Specify period of input clock

      CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of "NONE", "FIXED" or "VARIABLE" 

      CLK_FEEDBACK => "1X",         --  Specify clock feedback of "NONE", "1X" or "2X" 

      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or

                                             --     an integer from 0 to 15

      DLL_FREQUENCY_MODE => "LOW",     -- "HIGH" or "LOW" frequency mode for DLL

      DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE

      PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255

      STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE

   port map (

      CLK0 => CLOCK_OUT0_int,     -- 0 degree DCM CLK ouptput

      CLK180 => CLOCK_OUT180_int, -- 180 degree DCM CLK output

      CLK270 => open, -- 270 degree DCM CLK output

      CLK2X => open,   -- 2X DCM CLK output

      CLK2X180 => open, -- 2X, 180 degree DCM CLK out

      CLK90 => open,   -- 90 degree DCM CLK output

      CLKDV => open,   -- Divided DCM CLK out (CLKDV_DIVIDE)

      CLKFX => open,   -- DCM CLK synthesis out (M/D)

      CLKFX180 => open, -- 180 degree CLK synthesis out

      LOCKED => open, -- DCM LOCK status output

      PSDONE => open, -- Dynamic phase adjust done output

      STATUS => open, -- 8-bit DCM status bits output

      CLKFB => CLKFB_in,   -- DCM clock feedback

      CLKIN => CLOCK_INT,   -- Clock input (from IBUFG, BUFG or DCM)

      PSCLK => open,   -- Dynamic phase adjust clock input

      PSEN => open,     -- Dynamic phase adjust enable input

      PSINCDEC => open, -- Dynamic phase adjust increment/decrement

      RST => DCM_RESET        -- DCM asynchronous reset input

   );

--CLOCK_OUT180 <= CLOCK_OUT180_out;

--CLOCK_OUT0 <= CLOCK_OUT0_out;

--F : IDDR2

--generic map (

--   DDR_ALIGNMENT => "NONE", -- Sets output alignment 

--                            -- to "NONE", "C0" or "C1"

--   INIT_Q0 => '0', -- Sets initial state of the Q0  

--                   --   output to ?0? or ?1?

--   INIT_Q1 => '0', -- Sets initial state of the Q1 

--                   --   output to ?0? or ?1?

--   SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" 

--                      --   set/reset

--port map (

--   Q0 => DATA_OUTQ0, -- 1-bit output captured with C0 clock

--   Q1 => DATA_OUTQ1, -- 1-bit output captured with C1 clock

--   C0 => CLOCK_OUT0_int, -- 1-bit clock input

--   C1 => CLOCK_OUT180_int, -- 1-bit clock input

--   CE => IDDR2_CE, -- 1-bit clock enable input

--   D => DATA_INT,   -- 1-bit DDR data input

--   R => DDR_RESET,   -- 1-bit reset input

--   S => SET_DDR    -- 1-bit set input

--);

end Behavioral;