tb_test3.vhd

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-- Company: 

-- Engineer:

--

-- Create Date:   09:14:26 10/15/2009

-- Design Name:   

-- Module Name:   D:/PROJECTS/GiGe_Kamera/VHDL/Test S3A Starter/IDDR2_Daten_out/tb_test3.vhd

-- Project Name:  IDDR2_Daten_out

-- Target Device:  

-- Tool versions:  

-- Description:   

-- 

-- VHDL Test Bench Created by ISE for module: LVDS_CLOCK_IN

-- 

-- Dependencies:

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes: 

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test.  Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation 

-- simulation model.

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

Library UNISIM;

use UNISIM.vcomponents.all;

ENTITY tb_test3 IS

END tb_test3;

ARCHITECTURE behavior OF tb_test3 IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT LVDS_CLOCK_IN

    PORT(

         AFE_CLK_P : IN  std_logic;

         AFE_CLK_N : IN  std_logic;

         DCM_RESET : IN  std_logic;

         CLOCK_OUT0 : OUT  std_logic;

         CLOCK_OUT180 : OUT  std_logic

        );

    END COMPONENT;

   constant AFE_CLK_P_period : time := 10ns;

   --Inputs

   signal AFE_CLK_P : std_logic := '0';

   signal AFE_CLK_N : std_logic := '0';

   signal DCM_RESET : std_logic := '0';

   --Outputs

   signal CLOCK_OUT0 : std_logic;

   signal CLOCK_OUT180 : std_logic;

BEGIN

  -- Instantiate the Unit Under Test (UUT)

   uut: LVDS_CLOCK_IN PORT MAP (

          AFE_CLK_P => AFE_CLK_P,

          AFE_CLK_N => AFE_CLK_N,

          DCM_RESET => DCM_RESET,

          CLOCK_OUT0 => CLOCK_OUT0,

          CLOCK_OUT180 => CLOCK_OUT180

        );

   -- No clocks detected in port list. Replace <clock> below with 

   -- appropriate port name 

   AFE_CLK_P_process :process

   begin

    AFE_CLK_P <= '0';

    AFE_CLK_N <= '1';

    wait for AFE_CLK_P_period/2;

    AFE_CLK_P <= '1';

    AFE_CLK_N <= '0';

    wait for AFE_CLK_P_period/2;

   end process;

   -- Stimulus process

   stim_proc: process

   begin    

      -- hold reset state for 100ms.

      wait for 100ms;  

      wait for AFE_CLK_P_period*10;

      -- insert stimulus here 

      wait;

   end process;

END;