UART.vhd

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-- Company: 

-- Engineer: 

-- 

-- Create Date:    12:42:10 10/26/2009 

-- Design Name: 

-- Module Name:    UART - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity  UART is

  Generic ( Quarz_Taktfrequenz : integer   := 50000000;  -- Hertz               

            Baudrate : integer :=  7000000               -- Bits/Sec             

        );     

  Port ( 

      tx_data      : in   std_logic_vector (7 downto 0);

      TXD          : out  STD_LOGIC;           

         taste_start    : in   STD_LOGIC;           

         taste_stopp   : in   STD_LOGIC;

      CLK          : in   STD_LOGIC;

      RXD      : in   STD_LOGIC;

      RX_Data  : out  STD_LOGIC_VECTOR (7 downto 0));

      --RX_Busy  : out  STD_LOGIC);

end UART;

architecture Behavioral of UART is

signal tx_start : std_logic := '0';

signal tx_busy  : std_logic := '0';

--signal tx_data  : std_logic_vector  (7 downto 0) := x"F0";

signal txsr     : std_logic_vector  (9 downto 0);

signal txbitcnt : integer range 0 to 10 := 10;

signal txcnt    : integer range 0 to (Quarz_Taktfrequenz/Baudrate);

signal txd_tmp   :std_logic := '0';

signal rxd_sr    : std_logic_vector (3 downto 0) := "1111";  -- Flankenerkennung und Eintakten

signal rxsr      : std_logic_vector (7 downto 0) := "00000000";     -- 8 Datenbits

signal rxbitcnt   : integer range 0 to 9 := 9;

signal rxcnt      : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1; 

begin 

-- Verwaltung

process begin

   wait until rising_edge(CLK);

   if (taste_start='1') then -- Daten = 0xF0

--      tx_data <= x"F0";

    tx_start <= '1';

   end if;

   if (taste_stopp='1') then -- Stoppen

      tx_start <= '0';

   end if;

end process;

-- Senden

TXD     <= txsr(txsr'left);

txd_tmp   <= txsr(0);

process begin

   wait until rising_edge(CLK);

   if (tx_start = '1' and tx_busy = '0') then   -- dauernd senden, solange tx_start aktiv

      txcnt    <= 0;                            -- Zähler initialisieren         

      txbitcnt <= 0;                               

      txsr     <= '0' & tx_data & '1';          -- Startbit, 8 Datenbits, Stopbit      

  else

      if txcnt < ((Quarz_Taktfrequenz/Baudrate))then            

         txcnt <= txcnt+1;

      else  -- nächstes Bit ausgeben              

         if (txbitcnt<10) then              

            txcnt    <= 0;              

            txbitcnt <= txbitcnt+1;              

            txsr     <= txsr(txsr'left-1 downto 1) & '1';  

         end if;         

      end if;      

  end if;

   if (txbitcnt<10) then

    tx_busy <= '1';

    else tx_busy <='0';

  end if;

end process;

-- Empfangen

process begin

wait until rising_edge(CLK);      

rxd_sr <= rxd_sr(rxd_sr'left-1 downto 0) & txd_tmp;      

  if (rxbitcnt<9) then    -- Empfang läuft         

    if(rxcnt<(Quarz_Taktfrequenz/Baudrate)-1) then             

      rxcnt <= rxcnt+1;         

      else rxcnt      <= 0;             

          rxbitcnt <= rxbitcnt+1;            

          rxsr     <= rxd_sr(rxd_sr'left-1) & rxsr(rxsr'left downto 1); -- rechts schieben, weil LSB first         

    end if;      

    else -- warten auf Startbit         

    if (rxd_sr(3 downto 2) = "10") then                 -- fallende Flanke Startbit            

      rxcnt    <= ((Quarz_Taktfrequenz/Baudrate)-1)/2; -- erst mal nur halbe Bitzeit abwarten            

      rxbitcnt <= 0;         

    end if;      

  end if;   

end process;   

RX_Data <= rxsr;  

--RX_Busy <= '1' when (rxbitcnt<9) else '0';

end Behavioral;