UART.vhd


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----------------------------------------------------------------------------------

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-- Company: 

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-- Engineer: 

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-- 

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-- Create Date:    12:42:10 10/26/2009 

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-- Design Name: 

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-- Module Name:    UART - Behavioral 

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-- Project Name: 

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-- Target Devices: 

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-- Tool versions: 

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-- Description: 

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--

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-- Dependencies: 

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--

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-- Revision: 

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-- Revision 0.01 - File Created

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-- Additional Comments: 

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--

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----------------------------------------------------------------------------------

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_ARITH.ALL;

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use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

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---- any Xilinx primitives in this code.

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--library UNISIM;

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--use UNISIM.VComponents.all;

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entity  UART is

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  Generic ( Quarz_Taktfrequenz : integer   := 50000000;  -- Hertz               

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            Baudrate : integer :=  12000000              -- Bits/Sec             

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        );     

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  Port ( 

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      tx_data      : in   std_logic_vector (7 downto 0);

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      TXD          : out  STD_LOGIC;           

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         taste_start    : in   STD_LOGIC;           

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         taste_stopp   : in   STD_LOGIC;

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      CLK          : in   STD_LOGIC;

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      RXD      : in   STD_LOGIC;

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      RX_Data  : out  STD_LOGIC_VECTOR (7 downto 0));

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      --RX_Busy  : out  STD_LOGIC);

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end UART;

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architecture Behavioral of UART is

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signal tx_start : std_logic := '0';

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signal tx_busy  : std_logic := '0';

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--signal tx_data  : std_logic_vector  (7 downto 0);-- := x"F0";

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signal txsr     : std_logic_vector  (9 downto 0):= (others=>'1');

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signal txbitcnt : integer range 0 to 10 := 10;

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signal txcnt    : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1;

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signal txd_tmp   :std_logic := '0';

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--signal rxd_sr    : std_logic_vector (3 downto 0) := "1111";  -- Flankenerkennung und Eintakten

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signal rxd_sr    : std_logic_vector (1 downto 0) := "11";  -- Flankenerkennung und Eintakten

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signal rxsr      : std_logic_vector (7 downto 0) := "00000000";     -- 8 Datenbits

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signal rxbitcnt   : integer range 0 to 9 := 9;

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signal rxcnt      : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1; 

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begin 

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-- Verwaltung

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process begin

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   wait until rising_edge(CLK);

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   if (taste_start='1') then     -- Daten = 0xF0

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--      tx_data <= x"F0";

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    tx_start <= '1';

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   end if;

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   if (taste_stopp='1') then     -- Stoppen

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      tx_start <= '0';

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   end if;

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end process;

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-- Senden

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TXD     <= txsr(txsr'left);

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txd_tmp   <= txsr(txsr'left);

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process begin

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   wait until rising_edge(CLK);

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   if (tx_start = '1' and tx_busy = '0') then   -- dauernd senden, solange tx_start aktiv

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      txcnt    <= 0;                            -- Zähler initialisieren         

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      txbitcnt <= 0;                               

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      txsr     <= '0' & tx_data & '1';          -- Startbit, 8 Datenbits, Stopbit      

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  else

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      if txcnt < ((Quarz_Taktfrequenz/Baudrate)-1)then            

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         txcnt <= txcnt+1;

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      else  -- nächstes Bit ausgeben              

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         if (txbitcnt < 10) then              

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            txcnt    <= 0;              

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            txbitcnt <= txbitcnt+1;              

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            txsr     <= txsr(txsr'left-1 downto 1) & '1';  --txsr     <= txsr(txsr'left-1 downto 1) & '1'; 

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         end if;         

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      end if;      

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  end if;

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   if (txbitcnt < 10) then

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    tx_busy <= '1';

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    else tx_busy <='0';

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  end if;

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end process;

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-- Empfangen

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process begin

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wait until rising_edge(CLK);      

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--rxd_sr <= rxd_sr(rxd_sr'left-1 downto 0) & txd_tmp;

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rxd_sr <= rxd_sr(0) & txd_tmp;      

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  if (rxbitcnt < 9) then    -- Empfang läuft         

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    if(rxcnt < (Quarz_Taktfrequenz/Baudrate)-1) then             

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      rxcnt <= rxcnt+1;         

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      else rxcnt      <= 0;             

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          rxbitcnt <= rxbitcnt+1;            

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          --rxsr     <= rxd_sr(rxd_sr'left-1) & rxsr(rxsr'left downto 1);   -- rechts schieben, weil LSB first

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          --rxsr     <= rxd_sr(rxd_sr'left-1) & rxsr(1);               -- rechts schieben, weil LSB first 

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          rxsr     <= rxd_sr(1) & rxsr(rxsr'left downto 1);            -- rechts schieben, weil LSB first

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    end if;      

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    else -- warten auf Startbit         

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    --if (rxd_sr(3 downto 2) = "10") then                               -- fallende Flanke Startbit 

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    if (rxd_sr = "10") then    

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      --rxcnt    <= ((Quarz_Taktfrequenz/Baudrate)-1)/2;               -- erst mal nur halbe Bitzeit abwarten(bei langsamaren Frequenzen (7 MBit/s)            

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      rxcnt <= 2;                                          -- erst mal nur halbe Bitzeit abwarten (weil hohe Bitrate)

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      rxbitcnt <= 0;         

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    end if;      

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  end if;   

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end process;   

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RX_Data <= rxsr;  

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--RX_Busy <= '1' when (rxbitcnt<9) else '0';

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end Behavioral;