wrapper.vhd

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-- Company: 

-- Engineer: 

-- 

-- Create Date:    00:52:54 06/14/2009 

-- Design Name: 

-- Module Name:    wrapper - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

entity wrapper is

    Port ( CLK     : in   STD_LOGIC;

           CLK35     : in   STD_LOGIC;

           CLK35N   : in   STD_LOGIC;

        RST      : in   STD_LOGIC;  

           DataIn   : in   STD_LOGIC_VECTOR (20 downto 0);

           TxOUT    : out  STD_LOGIC_VECTOR (2 downto 0);

           TxCLK    : out  STD_LOGIC);

end wrapper;

architecture Behavioral of wrapper is

Signal RST_Int                : STD_LOGIC:='1';

Signal CLK_Edge1, Stop          : STD_LOGIC:='1';

Signal Data1, Data2            : STD_LOGIC_VECTOR(20 downto 0);

Signal ShiftClkp, ShiftClkn      : STD_LOGIC_VECTOR( 6 downto 0);

Signal Shift0p, Shift0n          : STD_LOGIC_VECTOR( 6 downto 0);

Signal Shift0p_load, Shift0n_load  : STD_LOGIC_VECTOR( 6 downto 0);

Signal Shift1p, Shift1n          : STD_LOGIC_VECTOR( 6 downto 0);

Signal Shift1p_load, Shift1n_load  : STD_LOGIC_VECTOR( 6 downto 0);

Signal Shift2p, Shift2n          : STD_LOGIC_VECTOR( 6 downto 0);

Signal Shift2p_load, Shift2n_load  : STD_LOGIC_VECTOR( 6 downto 0);

Signal Shift_Count_P, Shift_Count_N  : integer range 0 to 6:=6;

Signal DataTxCLK              : STD_LOGIC_VECTOR( 1 downto 0):=(others=>'0');  -- Signal vom Wrapper zum DDR-FF für den Takt

Signal DataTxOUT              : STD_LOGIC_VECTOR( 5 downto 0):=(others=>'0');  -- Signal vom Wrapper zum DDR-FF für die Daten

  COMPONENT FDDRCPE

   port (Q           : out STD_ULOGIC;

         C0         : in STD_ULOGIC;

         C1         : in STD_ULOGIC;

         CE         : in STD_ULOGIC;

         CLR         : in STD_ULOGIC;

         D0         : in STD_ULOGIC;

         D1         : in STD_ULOGIC;

         PRE         : in STD_ULOGIC);

  END COMPONENT;

begin

-- Synchrones Reset(Start)-Signal

process(CLK35)

begin

if rising_edge(CLK35) then

  CLK_Edge1    <= CLK;

  if RST = '1' then

    Stop      <= '1';

    RST_Int    <= '1';

  else

    if Stop = '1' then

     -- Damit der Start nach der Low=>High Flanke des CLK-Taktes anfängt.

    -- Die Takte sind per DCM synchron, deshalb sollte es keine Metazustände 

    -- durch die Takte geben, weil erst nach der steigenden Flanke von CLK abgefragt wird

    -- In 2 Normalen Takten sind 7 schnellere die alle 2Takte zum gleichen Zeitpunkt die 

    -- steigende Flanke haben.

      if CLK_Edge1 = '0' and CLK = '1' and RST = '0' then

        RST_Int    <= '0';

      Stop      <= '0';

      else

        RST_Int    <= '1';

      end if;

   end if;

  end if;

end if;

end process;

-- Datenzwischenspeicher, alle 2Takte werden die Daten in die 

-- Schieberegister geladen.

process(CLK, RST)

begin

if RST = '1' then

  Data1    <= "000000000000000000000";

  Data2    <= "000000000000000000000";

elsif rising_edge(CLK) then

  Data1    <= DataIn;

  Data2    <= Data1;

end if;

end process;

-- Zusammenstellung der Daten für die Schieberegister

-- Kanal 0

Shift0p_load  <= Data2( 5) & Data2( 3) & Data2( 1) & Data1( 6) & Data1( 4) & Data1( 2) & Data1( 0);

Shift0n_load   <= Data2( 6) & Data2( 4) & Data2( 2) & Data2( 0) & Data1( 5) & Data1( 3) & Data1( 1);

-- Kanal 1

Shift1p_load  <= Data2(12) & Data2(10) & Data2( 8) & Data1(13) & Data1(11) & Data1( 9) & Data1( 7);

Shift1n_load   <= Data2(13) & Data2(11) & Data2( 9) & Data2( 7) & Data1(12) & Data1(10) & Data1( 8);

-- Kanal 2

Shift2p_load  <= Data2(19) & Data2(17) & Data2(15) & Data1(20) & Data1(18) & Data1(16) & Data1(14);

Shift2n_load   <= Data2(20) & Data2(18) & Data2(16) & Data2(14) & Data1(19) & Data1(17) & Data1(15);

-- Schieberegister für normalen 3,5-fachen Takt

-- Das Signal auf dem normalen Takt wird als zweites ausgegeben

process(CLK35)

begin

if rising_edge(CLK35) then

  if RST_Int = '1' then

    Shift_Count_P    <= 6;

   ShiftClkp      <= "0000000";

   Shift0p        <= "0000000";

   Shift1p        <= "0000000";

   Shift2p        <= "0000000";

  else

    if Shift_Count_P = 6 then

      Shift_Count_P   <= 0;

     ShiftClkp    <= "1011001";

     Shift0p      <= Shift0p_load;

     Shift1p      <= Shift1p_load;

     Shift2p      <= Shift2p_load;

    else

      Shift_Count_P   <= Shift_Count_P + 1;

    ShiftClkp    <= ShiftClkp(5 downto 0) & '0';

      Shift0p      <= Shift0p(5 downto 0) & '0';

      Shift1p      <= Shift1p(5 downto 0) & '0';

      Shift2p      <= Shift2p(5 downto 0) & '0';

    end if;

  end if;

end if;

end process;

-- Datenzuweisung zu den DDR-Zellen

DataTxCLK(1)      <= ShiftClkp(6);

DataTxOUT(3)      <= Shift0p(6);

DataTxOUT(4)      <= Shift1p(6);

DataTxOUT(5)      <= Shift2p(6);

-- Schieberegister für negierten 3,5-fachen Takt

-- Das Signal auf dem negiertem Takt wird als erstes ausgegeben

process(CLK35N)

begin

if rising_edge(CLK35N) then

  if RST_Int = '1' then

    Shift_Count_N    <= 6;

   ShiftClkn      <= "0000000";

   Shift0n        <= "0000000";

   Shift1n        <= "0000000";

   Shift2n        <= "0000000";

  else

    if Shift_Count_N = 6 then

      Shift_Count_N   <= 0;

     ShiftClkn    <= "1001101";

     Shift0n      <= Shift0n_load;

     Shift1n      <= Shift1n_load;

     Shift2n      <= Shift2n_load;

    else

      Shift_Count_N   <= Shift_Count_N + 1;

    ShiftClkn    <= ShiftClkn(5 downto 0) & '0';

      Shift0n      <= Shift0n(5 downto 0) & '0';

      Shift1n      <= Shift1n(5 downto 0) & '0';

      Shift2n      <= Shift2n(5 downto 0) & '0';

    end if;

  end if;

end if;

end process;

-- Datenzuweisung zu den DDR-Zellen

DataTxCLK(0)      <= ShiftClkn(6);

DataTxOUT(0)      <= Shift0n(6);

DataTxOUT(1)      <= Shift1n(6);

DataTxOUT(2)      <= Shift2n(6);

-- DDR Zelle TxCLK

   FDDRCPE_TxOUT : FDDRCPE

   port map (

      Q    => TxCLK,        -- Data output (connect directly to top-level port)

      C0    => CLK35,        -- 0 degree clock input

      C1    => CLK35N,        -- 180 degree clock input

      CE    => '1',          -- Clock enable input

      D0    => DataTxCLK(1),  -- Posedge data input

      D1    => DataTxCLK(0),  -- Negedge data input

      CLR  => '0',         -- Synchronous reset input

      PRE  => '0'           -- Synchronous preset input

   );

-- DDR Zelle TxOUT(i)

loop0 : for i in 0 to 2 generate 

   FDDRCPE_TxOUT : FDDRCPE

   port map (

      Q    => TxOUT(i),      -- Data output (connect directly to top-level port)

      C0    => CLK35,        -- 0 degree clock input

      C1    => CLK35N,        -- 180 degree clock input

      CE    => '1',          -- Clock enable input

      D0    => DataTxOUT(i+3),-- Posedge data input

      D1    => DataTxOUT(i),  -- Negedge data input

      CLR  => '0',         -- Synchronous reset input

      PRE  => '0'           -- Synchronous preset input

   );

end generate ;

end Behavioral;