top_level.vhd

library IEEE;

library UNISIM;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use UNISIM.vcomponents.all;

entity top_level is

    Port ( CLK_IN      : in  STD_LOGIC;

           taster1    : in   STD_LOGIC;

           taster2    : in   STD_LOGIC;

           taster3    : in   STD_LOGIC;

           taster4    : in   STD_LOGIC;

           TxCLK_p    : out STD_LOGIC;

           TxCLK_n    : out STD_LOGIC;

           TxOUT_p    : out STD_LOGIC_VECTOR( 2 downto 0);

           TxOUT_n    : out STD_LOGIC_VECTOR( 2 downto 0));

end top_level;

architecture Behavioral of top_level is

Signal TxCLK                  : STD_LOGIC:='0';                      -- Signal zum LVDS Transmitter

Signal TxOUT                  : STD_LOGIC_VECTOR( 2 downto 0):="000";      -- Signal zum LVDS Transmitter

Signal CLK35, CLK35N, CLK          : STD_LOGIC:='0';                      -- Intern verwendete Taktsignale

Signal DCM_NotReady, DCM_Ready35      : STD_LOGIC:='0';                      -- Signal, wenn die DCM eingerastet ist(Enable)

Signal RST_Data                : STD_LOGIC:='1';                      -- Synchrones Reset Signal

Signal DataIn                  : STD_LOGIC_VECTOR(20 downto 0);

--  COMPONENT dcm_clk

--  PORT(

--    CLKIN_IN : IN std_logic;          

--    CLKFX_OUT : OUT std_logic;

--    CLKIN_IBUFG_OUT : OUT std_logic;

--    CLK0_OUT : OUT std_logic;

--    LOCKED_OUT : OUT std_logic

--    );

--  END COMPONENT;

--  COMPONENT DCM_CLK35

--  PORT(

--    CLKIN_IN        : IN  STD_LOGIC; 

--    CLKFX_OUT      : OUT STD_LOGIC;

--    CLKFX180_OUT    : OUT STD_LOGIC;

--    CLKIN_IBUFG_OUT  : OUT STD_LOGIC;

--    CLK0_OUT        : OUT STD_LOGIC;

--    LOCKED_OUT      : OUT STD_LOGIC

--    );

--  END COMPONENT;

  COMPONENT dcm_all

  PORT(

    U1_CLKIN_IN : IN std_logic;

    U1_RST_IN : IN std_logic;          

    U1_CLKDV_OUT : OUT std_logic;

    U1_CLKIN_IBUFG_OUT : OUT std_logic;

    U1_CLK0_OUT : OUT std_logic;

    U2_CLKFX_OUT : OUT std_logic;

    U2_CLKFX180_OUT : OUT std_logic;

    U2_CLK0_OUT : OUT std_logic;

    U2_LOCKED_OUT : OUT std_logic

    );

  END COMPONENT;

  COMPONENT OBUFDS

  port (O          : out STD_ULOGIC;

      OB          : out STD_ULOGIC;

      I          : in STD_ULOGIC);

  END COMPONENT;

  COMPONENT Display

    Port ( clk_in      : in   STD_LOGIC;

        RST        : in   STD_LOGIC;

          taster1    : in   STD_LOGIC;

          taster2    : in   STD_LOGIC;

          taster3    : in   STD_LOGIC;

          taster4    : in   STD_LOGIC;

           red       : out  STD_LOGIC_VECTOR (5 downto 0);

           blue       : out  STD_LOGIC_VECTOR (5 downto 0);

           green       : out  STD_LOGIC_VECTOR (5 downto 0);

           hsync       : out  STD_LOGIC;

           vsync       : out  STD_LOGIC;

           enable     : out  STD_LOGIC);

  END COMPONENT;

  COMPONENT wrapper

    Port ( CLK       : in  STD_LOGIC;

           CLK35       : in  STD_LOGIC;

           CLK35N     : in  STD_LOGIC;

        RST        : in  STD_LOGIC;  

           DataIn     : in  STD_LOGIC_VECTOR (20 downto 0);

           TxOUT      : out  STD_LOGIC_VECTOR (2 downto 0);

           TxCLK      : out  STD_LOGIC);

  END COMPONENT;

begin

---- DCM für 40MHz

--  Inst_DCM_CLK: DCM_CLK PORT MAP(

--    CLKIN_IN       => CLK_IN,    -- 80MHz Takt in

--    CLKFX_OUT      => CLK40,    -- 40MHz Takt aus

--    CLKIN_IBUFG_OUT  => open,

--    CLK0_OUT        => open,

--    LOCKED_OUT       => open

--  );

-- DCM für 3,5 fachen Tackt = 210Mhz

--  Inst_DCM_CLK35: DCM_CLK35 PORT MAP(

--    CLKIN_IN       => CLK40,    -- 60MHz Takt in

--    CLKFX_OUT      => CLK35,    -- 210MHz Takt aus

--    CLKFX180_OUT    => CLK35N,    -- 210MHz negiert Takt aus

--    CLKIN_IBUFG_OUT  => open,

--    CLK0_OUT        => CLK,      -- 60MHz gepuffert syncron zum 210MHz Takt aus

--    LOCKED_OUT       => DCM_Ready35

--  );

  Inst_dcm_all: dcm_all PORT MAP(

    U1_CLKIN_IN     => CLK_IN,

    U1_RST_IN       => '0',

    U1_CLKDV_OUT     => open,

    U1_CLKIN_IBUFG_OUT=> open,

    U1_CLK0_OUT     => open,

    U2_CLKFX_OUT     => CLK35,

    U2_CLKFX180_OUT   => CLK35N,

    U2_CLK0_OUT     => CLK,

    U2_LOCKED_OUT     => DCM_Ready35

  );

-- Wrapper

  Inst_wrapper: wrapper PORT MAP(

      CLK          =>CLK,

      CLK35          =>CLK35,

      CLK35N        =>CLK35N,

    RST          =>RST_Data,

      DataIn        =>DataIn,

      TxOUT          =>TxOUT,

      TxCLK          =>TxCLK

  );

-- Display

  Inst_Display: Display PORT MAP(

    clk_in        =>CLK,

    RST          => '0',

    taster1        =>taster1,

    taster2        =>taster2,

    taster3        =>taster3,

    taster4        =>taster4,

    red          =>DataIn( 5 downto  0),

    blue          =>DataIn(11 downto  6),

    green          =>DataIn(17 downto 12),

    hsync          =>DataIn(18),

    vsync          =>DataIn(19),

    enable        =>DataIn(20)

  );  

-- LVDS Transmitter Instanzieren CLK

   OBUFDS_TxCLK : OBUFDS

   port map (

      O  => TxCLK_p,    -- Diff_p output

      OB => TxCLK_n,    -- Diff_n output

      I  => TxCLK       -- Buffer input 

   );

-- LVDS Transmitter Instanzieren TxOUT(i)

loop0 : for i in 0 to 2 generate 

   OBUFDS_TxOUT : OBUFDS

   port map (

      O  => TxOUT_p(i),    -- Diff_p output

      OB => TxOUT_n(i),     -- Diff_n output

      I  => TxOUT(i)       -- Buffer input 

   );

end generate ;

-- Für das Ready Signal der DCM als Reset

   DCM_NotReady <= (not DCM_Ready35);

-- Generiert ein syncrones Reset-Signal für den Sendetakt

process(CLK)

begin

if rising_edge(CLK) then

  RST_Data <= DCM_NotReady;

end if;

end process;

end Behavioral;