1 | ----------------------------------------------------------------------------------
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2 | -- Company: www.Circuit-Break.de
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3 | -- Engineer: Jens Weiss
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4 | --
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5 | -- Create Date: 10:14:32 02/23/2024
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6 | -- Design Name:
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7 | -- Module Name: Opcode_memory - Behavioral
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8 | -- Project Name:
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9 | -- Target Devices:
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10 | -- Tool versions:
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11 | -- Description:
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12 | --
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13 | -- Dependencies:
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14 | --
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15 | -- Revision:
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16 | -- Revision 0.01 - File Created
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17 | -- Additional Comments:
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18 | --
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19 | ----------------------------------------------------------------------------------
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20 | library IEEE;
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21 | use IEEE.STD_LOGIC_1164.ALL;
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22 | use IEEE.NUMERIC_STD.ALL;
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23 |
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24 |
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25 | entity Opcode_memory is
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26 | Generic(ADRESSWIDTH : natural := 5; --memory depth = 2^ADDRESSWIDTH
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27 | DATAWIDTH : natural := 8);
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28 |
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29 | Port ( clk : in std_logic;
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30 | A : in std_logic_vector(ADRESSWIDTH-1 downto 0);
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31 | Dout : out std_logic_vector(DATAWIDTH-1 downto 0)
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32 | );
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33 | end Opcode_memory;
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34 |
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35 | architecture Behavioral of Opcode_memory is
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36 |
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37 | signal RomAddr : integer range 0 to (2**ADRESSWIDTH)-1;
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38 | type Rom is array (0 to (2**ADRESSWIDTH)-1) of STD_LOGIC_VECTOR(DATAWIDTH-1 downto 0);
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39 | constant Parameter_Rom : Rom := (
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40 | -- Integrator LT1
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41 | "00101000", -- Ocode: "00101 000" Parameter: b1 | Dataselect: 000 (data_in)
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42 | "00000001", -- Ocode: "00000 001" Parameter: a1 | Dataselect: 001 (int_data_out)
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43 | "10100011", -- Ocode: "10100 011" Parameter:e21 | Dataselect: 011 (LT2_out)
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44 | "10101100", -- Ocode: "10101 100" Parameter:e31 | Dataselect: 100 (LT3_out)
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45 | "10111101", -- Ocode: "10111 101" Parameter:e41 | Dataselect: 101 (LT4_out)
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46 | -- Integrator LT2
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47 | "00110000", -- Ocode: "00110 000" Parameter: b2 | Dataselect: 000 (data_in)
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48 | "00001001", -- Ocode: "00001 001" Parameter: a2 | Dataselect: 001 (int_data_out)
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49 | "01010010", -- Ocode: "01010 010" Parameter: c1 | Dataselect: 010 (LT1_out)
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50 | "10110100", -- Ocode: "10110 100" Parameter:e32 | Dataselect: 100 (LT3_out)
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51 | "11000101", -- Ocode: "11000 101" Parameter:e42 | Dataselect: 101 (LT4_out)
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52 | -- Integrator LT3
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53 | "00111000", -- Ocode: "00111 000" Parameter: b3 | Dataselect: 000 (data_in)
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54 | "00010001", -- Ocode: "00010 001" Parameter: a3 | Dataselect: 001 (int_data_out)
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55 | "01110010", -- Ocode: "01110 010" Parameter:d13 | Dataselect: 010 (LT1_out)
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56 | "01011011", -- Ocode: "01011 011" Parameter: c2 | Dataselect: 011 (LT2_out)
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57 | "11001101", -- Ocode: "11001 101" Parameter:e43 | Dataselect: 101 (LT4_out)
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58 | -- Integrator LT4
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59 | "01000000", -- Ocode: "01000 000" Parameter: b4 | Dataselect: 000 (data_in)
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60 | "00011001", -- Ocode: "00011 001" Parameter: a4 | Dataselect: 001 (int_data_out)
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61 | "01111010", -- Ocode: "01111 010" Parameter:d14 | Dataselect: 010 (LT1_out)
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62 | "10001011", -- Ocode: "10001 011" Parameter:d24 | Dataselect: 011 (LT2_out)
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63 | "01100100", -- Ocode: "01100 100" Parameter: c3 | Dataselect: 100 (LT3_out)
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64 | -- Output/to Quantizer
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65 | "01001000", -- Ocode: "01001 000" Parameter: b5 | Dataselect: 000 (data_in)
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66 | "00100001", -- Ocode: "00100 001" Parameter: a5 | Dataselect: 001 (int_data_out)
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67 | "10000010", -- Ocode: "10000 010" Parameter:d15 | Dataselect: 010 (LT1_out)
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68 | "10010011", -- Ocode: "10010 011" Parameter:d25 | Dataselect: 011 (LT2_out)
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69 | "10011100", -- Ocode: "10011 100" Parameter:d35 | Dataselect: 100 (LT3_out)
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70 | "01101101", -- Ocode: "01101 101" Parameter: c4 | Dataselect: 101 (LT4_out)
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71 | others => "00000000"
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72 | );
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73 |
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74 | begin
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75 | --BROM
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76 | process begin
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77 | wait until rising_edge(clk);
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78 | RomAddr <= to_integer(unsigned(A)); -- clocked address --> BRAM
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79 | end process;
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80 | --Dout <= Parameter_Rom(to_integer(unsigned(A)));
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81 | Dout <= std_logic_vector(Parameter_Rom(RomAddr));
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82 |
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83 | end Behavioral;
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