Parameter_memory.vhd


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----------------------------------------------------------------------------------
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-- Company: www.Circuit-Break.de
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-- Engineer: Jens Weiss
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-- 
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-- Create Date:    13:36:13 02/21/2024 
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-- Design Name: 
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-- Module Name:    Parameter_memory - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity Parameter_memory is
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  Generic(ADRESSWIDTH : natural := 5;  --memory depth = 2^ADDRESSWIDTH
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         DATAWIDTH : natural := 16);
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  Port  (  clk  : in std_logic;
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        A    : in std_logic_vector(ADRESSWIDTH-1 downto 0);
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        Dout  : out std_logic_vector(DATAWIDTH-1 downto 0)
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      );
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end Parameter_memory;
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architecture Behavioral of Parameter_memory is
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  signal RomAddr  : integer range 0 to (2**ADRESSWIDTH)-1;  
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  type Rom is array (0 to (2**ADRESSWIDTH)-1) of signed (DATAWIDTH-1 downto 0); 
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  constant Parameter_Rom : Rom := (
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   x"C0F8",  -- Parameter: a1  | Adress: 00000
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  x"0000",  -- Parameter: a2  | Adress: 00001
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  x"0000",  -- Parameter: a3  | Adress: 00010
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  x"0000",  -- Parameter: a4  | Adress: 00011
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  x"F6CE",  -- Parameter: a5  | Adress: 00100
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  x"3F08",  -- Parameter: b1  | Adress: 00101
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  x"0000",  -- Parameter: b2  | Adress: 00110
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  x"0000",  -- Parameter: b3  | Adress: 00111
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  x"0000",  -- Parameter: b4  | Adress: 01000
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  x"2999",  -- Parameter: b5  | Adress: 01001
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  x"0000",  -- Parameter: c1  | Adress: 01010
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  x"0000",  -- Parameter: c2  | Adress: 01011
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  x"0000",  -- Parameter: c3  | Adress: 01100
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  x"0000",  -- Parameter: c4  | Adress: 01101
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  x"0000",  -- Parameter: d13  | Adress: 01110
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  x"0000",  -- Parameter: d14  | Adress: 01111
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   x"20A8",  -- Parameter: d15  | Adress: 10000
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  x"0000",  -- Parameter: d24  | Adress: 10001
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  x"0000",  -- Parameter: d25  | Adress: 10010
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  x"0000",  -- Parameter: d35  | Adress: 10011
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  x"0000",  -- Parameter: e21  | Adress: 10100
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  x"0000",  -- Parameter: e31  | Adress: 10101
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  x"0000",  -- Parameter: e32  | Adress: 10110
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  x"0000",  -- Parameter: e41  | Adress: 10111
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  x"0000",  -- Parameter: e42  | Adress: 11000
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  x"0000",  -- Parameter: e43  | Adress: 11001
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  x"0000",  -- Parameter: dummy  | Adress: 11010
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  x"0000",  -- Parameter: dummy  | Adress: 11011
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  x"0000",  -- Parameter: dummy  | Adress: 11100
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  x"0000",  -- Parameter: dummy  | Adress: 11101
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  x"0000",  -- Parameter: dummy  | Adress: 11110
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  x"0000"    -- Parameter: dummy  | Adress: 11111
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  );
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begin
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  --BROM      
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   process begin
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     wait until rising_edge(clk);
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     RomAddr <= to_integer(unsigned(A)); -- clocked address --> BRAM
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   end process;
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   Dout <= std_logic_vector(Parameter_Rom(RomAddr));
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end Behavioral;