MAC_Unit.vhd

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-- Company: www.Circuit-Break.de

-- Engineer: Jens Weiss

-- 

-- Create Date:    10:49:11 02/27/2024 

-- Design Name: 

-- Module Name:    MAC_Unit - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity MAC_Unit is

  Generic(  DATA_WIDTH : integer := 26;

        PARAMETER_WIDTH : integer := 16;

        SCALE_FACTOR : integer := 14;

        ACCU_WIDTH : integer := 43

        );

    Port (  clk : in  std_logic;

        MAC_preload : in  std_logic;

        MAC_exec : in std_logic;

        MAC_Load : in std_logic_vector(DATA_WIDTH-1 downto 0);

        MAC_Din_a : in  std_logic_vector(DATA_WIDTH-1 downto 0);

        MAC_Din_b : in std_logic_vector(PARAMETER_WIDTH-1 downto 0);

        MAC_Dout : out  std_logic_vector(DATA_WIDTH-1 downto 0));

end MAC_Unit;

architecture Behavioral of MAC_Unit is

signal MAC_Accu : signed(ACCU_WIDTH-1 downto 0);

begin

  process

  begin

    wait until rising_edge(clk);    

    if(MAC_preload = '1') then

      MAC_Accu <= resize(signed(MAC_Load), ACCU_WIDTH);

    else      

      if(MAC_exec = '1') then

        MAC_Accu <= (((signed(MAC_Din_a) * signed(MAC_Din_b)) / 2**SCALE_FACTOR)) + MAC_Accu;

      end if;

    end if;

  end process;

  MAC_DOUT <= std_logic_vector(resize(MAC_Accu, DATA_WIDTH));

end Behavioral;