1 | #include <cstdint>
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2 | #include <initializer_list>
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3 |
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4 | #include "driver/flash_loader_defs.hpp"
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5 |
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6 | #define NRF_FLASH_LOADER_DEBUG 0
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7 |
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8 | #ifdef __cplusplus
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9 | #define __I volatile /*!< Defines 'read only' permissions */
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10 | #else
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11 | #define __I volatile const /*!< Defines 'read only' permissions */
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12 | #endif
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13 | #define __O volatile /*!< Defines 'write only' permissions */
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14 | #define __IO volatile /*!< Defines 'read / write' permissions */
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15 |
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16 | /* following defines should be used for structure members */
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17 | #define __IM volatile const /*! Defines 'read only' structure member permissions */
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18 | #define __OM volatile /*! Defines 'write only' structure member permissions */
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19 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */
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20 |
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21 | /* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
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22 | #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
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23 | #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
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24 | #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
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25 | #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
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26 |
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27 | /* Peripheral: NVMC */
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28 | /* Description: Non Volatile Memory Controller */
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29 |
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30 | /* Register: NVMC_READY */
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31 | /* Description: Ready flag */
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32 |
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33 | /* Bit 0 : NVMC is ready or busy */
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34 | #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
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35 | #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
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36 | #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
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37 | #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
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38 |
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39 | /* Register: NVMC_CONFIG */
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40 | /* Description: Configuration register */
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41 |
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42 | /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
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43 | #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
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44 | #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
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45 | #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
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46 | #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
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47 | #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
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48 |
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49 | /* Register: NVMC_ERASEPAGE */
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50 | /* Description: Register for erasing a page in Code area */
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51 |
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52 | /* Bits 31..0 : Register for starting erase of a page in Code area */
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53 | #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
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54 | #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
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55 |
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56 | /* Register: NVMC_ERASEPCR1 */
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57 | /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
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58 |
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59 | /* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
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60 | #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
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61 | #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
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62 |
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63 | /* Register: NVMC_ERASEALL */
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64 | /* Description: Register for erasing all non-volatile user memory */
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65 |
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66 | /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
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67 | #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
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68 | #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
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69 | #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
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70 | #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
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71 |
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72 | /* Register: NVMC_ERASEPCR0 */
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73 | /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
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74 |
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75 | /* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
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76 | #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
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77 | #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
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78 |
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79 | /* Register: NVMC_ERASEUICR */
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80 | /* Description: Register for erasing User Information Configuration Registers */
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81 |
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82 | /* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
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83 | #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
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84 | #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
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85 | #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
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86 | #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
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87 |
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88 | /* Register: NVMC_ICACHECNF */
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89 | /* Description: I-Code cache configuration register. */
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90 |
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91 | /* Bit 8 : Cache profiling enable */
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92 | #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
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93 | #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
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94 | #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
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95 | #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
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96 |
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97 | /* Bit 0 : Cache enable */
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98 | #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
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99 | #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
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100 | #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
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101 | #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
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102 |
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103 | /* Register: NVMC_IHIT */
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104 | /* Description: I-Code cache hit counter. */
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105 |
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106 | /* Bits 31..0 : Number of cache hits */
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107 | #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
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108 | #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
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109 |
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110 | /* Register: NVMC_IMISS */
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111 | /* Description: I-Code cache miss counter. */
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112 |
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113 | /* Bits 31..0 : Number of cache misses */
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114 | #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
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115 | #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
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116 |
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117 | __attribute__((always_inline)) static inline void __ISB(void)
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118 | {
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119 | __asm volatile ("isb 0xF":::"memory");
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120 | }
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121 |
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122 |
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123 | /**
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124 | \brief Data Synchronization Barrier
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125 | \details Acts as a special kind of Data Memory Barrier.
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126 | It completes when all explicit memory accesses before this instruction complete.
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127 | */
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128 | __attribute__((always_inline)) static inline void __DSB(void)
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129 | {
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130 | __asm volatile ("dsb 0xF":::"memory");
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131 | }
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132 |
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133 | /**
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134 | * @brief Block Protect (BPROT)
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135 | */
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136 |
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137 | typedef struct { /*!< (@ 0x40000000) BPROT Structure */
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138 | __IM uint32_t RESERVED[384];
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139 | __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */
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140 | __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */
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141 | __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface
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142 | mode */
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143 | __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */
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144 | __IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */
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145 | __IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */
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146 | } NRF_BPROT_Type; /*!< Size = 1560 (0x618) */
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147 |
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148 | /**
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149 | * @brief Non Volatile Memory Controller (NVMC)
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150 | */
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151 |
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152 | typedef struct { /*!< (@ 0x4001E000) NVMC Structure */
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153 | __IM uint32_t RESERVED[256];
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154 | __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */
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155 | __IM uint32_t RESERVED1[64];
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156 | __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */
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157 |
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158 | union {
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159 | __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in Code area */
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160 | __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a
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161 | page in Code area. Equivalent to ERASEPAGE. */
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162 | };
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163 | __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */
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164 | __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a
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165 | page in Code area. Equivalent to ERASEPAGE. */
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166 | __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing User Information Configuration
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167 | Registers */
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168 | __IM uint32_t RESERVED2[10];
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169 | __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-Code cache configuration register. */
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170 | __IM uint32_t RESERVED3;
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171 | __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-Code cache hit counter. */
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172 | __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. */
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173 | } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */
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174 |
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175 | typedef struct { /*!< (@ 0x50000000) P0 Structure */
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176 | __IM uint32_t RESERVED[321];
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177 | __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */
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178 | __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */
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179 | __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */
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180 | __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */
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181 | __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */
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182 | __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */
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183 | __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */
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184 | __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that
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185 | have met the criteria set in the PIN_CNF[n].SENSE
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186 | registers */
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187 | __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour
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188 | and LDETECT mode */
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189 | __IM uint32_t RESERVED1[118];
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190 | __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO
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191 | pins */
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192 | } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */
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193 |
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194 | #define NRF_NVMC_BASE 0x4001E000UL
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195 | #define NRF_BPROT_BASE 0x40000000UL
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196 | #define NRF_P0_BASE 0x50000000UL
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197 |
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198 | #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE)
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199 | #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE)
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200 | #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE)
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201 | #define NRF_GPIO ((NRF_GPIO_Type*) NRF_P0_BASE)
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202 |
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203 | /* Register: GPIO_PIN_CNF */
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204 | /* Description: Description collection[0]: Configuration of GPIO pins */
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205 |
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206 | /* Bits 17..16 : Pin sensing mechanism */
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207 | #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
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208 | #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
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209 | #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
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210 | #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
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211 | #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
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212 |
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213 | /* Bits 10..8 : Drive configuration */
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214 | #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
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215 | #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
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216 | #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
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217 | #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
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218 | #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
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219 | #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
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220 | #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
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221 | #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
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222 | #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
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223 | #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
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224 |
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225 | /* Bits 3..2 : Pull configuration */
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226 | #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
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227 | #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
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228 | #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
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229 | #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
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230 | #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
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231 |
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232 | /* Bit 1 : Connect or disconnect input buffer */
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233 | #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
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234 | #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
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235 | #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
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236 | #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
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237 |
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238 | /* Bit 0 : Pin direction. Same physical register as DIR register */
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239 | #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
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240 | #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
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241 | #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
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242 | #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
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243 |
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244 | #if NRF_FLASH_LOADER_DEBUG
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245 | static constexpr std::uint32_t debug_pin0 = 19;
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246 | static constexpr std::uint32_t debug_pin1 = 20;
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247 | static constexpr std::uint32_t debug_pin2 = 22;
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248 | static constexpr std::uint32_t debug_pin3 = 23;
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249 | static constexpr std::uint32_t all_debug_pin_mask =
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250 | ( 1 << debug_pin0 ) |
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251 | ( 1 << debug_pin1 ) |
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252 | ( 1 << debug_pin2 ) |
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253 | ( 1 << debug_pin3 );
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254 | #endif
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255 |
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256 | static constexpr std::uint32_t flash_driver_result_ok = 0;
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257 | static constexpr std::uint32_t flash_driver_result_error = 1;
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258 |
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259 | /**
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260 | * @brief writes a page of flash memory
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261 | *
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262 | * @param word_count size of flash memory / 4
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263 | * @param target_address start address of flash memory
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264 | * @param content_address start address, containing the content to be flashed
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265 | */
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266 | extern "C" std::uint32_t flash_loader(
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267 | std::uint32_t function,
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268 | std::uint32_t word_count,
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269 | std::uint32_t target_address,
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270 | std::uint32_t content_address )
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271 | {
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272 | bool result = true;
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273 |
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274 | # if NRF_FLASH_LOADER_DEBUG
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275 | for ( auto pin: { debug_pin0, debug_pin1, debug_pin2, debug_pin3 } )
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276 | NRF_GPIO->PIN_CNF[ pin ] =
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277 | ( GPIO_PIN_CNF_DRIVE_S0H1 << GPIO_PIN_CNF_DRIVE_Pos ) |
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278 | ( GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos );
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279 |
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280 | NRF_GPIO->OUTSET = 1 << debug_pin0;
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281 | # endif
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282 |
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283 | // disable cache
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284 | NRF_NVMC->ICACHECNF = 0;
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285 | // Disable Blockprotection
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286 | NRF_BPROT->DISABLEINDEBUG = BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk;
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287 |
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288 | if ( static_cast< driver::flash_loader_function >( function ) == driver::flash_loader_function::erase_all )
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289 | {
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290 | # if NRF_FLASH_LOADER_DEBUG
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291 | NRF_GPIO->OUTSET = 1 << debug_pin1;
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292 | # endif
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293 |
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294 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
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295 | __ISB();
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296 | __DSB();
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297 |
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298 | NRF_NVMC->ERASEALL = NVMC_ERASEALL_ERASEALL_Erase;
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299 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
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300 | ;
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301 |
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302 | # if NRF_FLASH_LOADER_DEBUG
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303 | NRF_GPIO->OUTCLR = 1 << debug_pin1;
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304 | NRF_GPIO->OUTCLR = 1 << debug_pin0;
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305 | # endif
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306 |
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307 | return flash_driver_result_ok;
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308 | }
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309 |
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310 | if ( static_cast< driver::flash_loader_function >( function ) == driver::flash_loader_function::flash_and_erase_block )
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311 | {
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312 | # if NRF_FLASH_LOADER_DEBUG
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313 | NRF_GPIO->OUTSET = 1 << debug_pin2;
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314 | # endif
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315 |
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316 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
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317 | __ISB();
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318 | __DSB();
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319 |
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320 | NRF_NVMC->ERASEPAGE = target_address;
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321 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
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322 | ;
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323 |
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324 | # if NRF_FLASH_LOADER_DEBUG
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325 | NRF_GPIO->OUTCLR = 1 << debug_pin2;
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326 | # endif
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327 | }
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328 |
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329 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
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330 | __ISB();
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331 | __DSB();
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332 |
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333 | for ( ; word_count && result; --word_count )
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334 | {
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335 | *reinterpret_cast< std::uint32_t* >( target_address ) =
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336 | *reinterpret_cast< const std::uint32_t* >( content_address );
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337 |
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338 | while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
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339 | ;
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340 |
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341 | result = *reinterpret_cast< std::uint32_t* >( target_address ) ==
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342 | *reinterpret_cast< const std::uint32_t* >( content_address );
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343 |
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344 | target_address += 4;
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345 | content_address += 4;
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346 | }
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347 |
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348 | NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
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349 | __ISB();
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350 | __DSB();
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351 |
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352 | # if NRF_FLASH_LOADER_DEBUG
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353 | NRF_GPIO->OUTCLR = 1 << debug_pin0;
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354 | # endif
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355 |
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356 | return result ? flash_driver_result_ok : flash_driver_result_error;
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357 | }
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