1 | ----------------------------------------------------------------------------------
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2 | -- Company:Zuritronic
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3 | -- Engineer:a.Kurka
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4 | --
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5 | -- Create Date: 06.05.2021 by a.kurka
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6 | -- Design Name: AS21
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7 | -- Module Name: arccos - Behavioral
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8 | -- modified : 09.05.2021 by a.kurka
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9 | --
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10 | ----------------------------------------------------------------------------------
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11 | library IEEE;
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12 | use IEEE.STD_LOGIC_1164.ALL;
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13 | use IEEE.STD_LOGIC_ARITH.ALL;
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14 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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15 |
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16 |
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17 | entity arcCosFP is
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18 | port( nrst : in std_logic;
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19 | clk : in std_logic;
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20 | ceacos : in std_logic;-- startimpuls afkt
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21 | ainp :in std_logic_vector(31 downto 0);-- input afkt FP format
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22 | acos :OUT std_logic_vector(31 downto 0):=X"00000000"-- output afkt FP format
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23 | );
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24 | end arcCosFP;
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25 |
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26 | architecture Behavioral of arcCosFP is
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27 |
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28 | COMPONENT afkt is
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29 | generic( P0:std_logic_vector(31 downto 0):=X"00000000";
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30 | P1:std_logic_vector(31 downto 0):=X"00000000";
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31 | P2:std_logic_vector(31 downto 0):=X"00000000";
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32 | Q0:std_logic_vector(31 downto 0):=X"00000000";
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33 | Q1:std_logic_vector(31 downto 0):=X"00000000";
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34 | Q2:std_logic_vector(31 downto 0):=X"00000000"
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35 | );
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36 | port( nrst : in std_logic;
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37 | clk : in std_logic;
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38 | ceafkt : in std_logic;-- startimpuls afkt
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39 | Xinp :in std_logic_vector(31 downto 0);-- input afkt FP format
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40 | aout :OUT std_logic_vector(31 downto 0)-- output afkt FP format
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41 | );
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42 | END COMPONENT;
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43 | -----------------------------------------
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44 | COMPONENT subFP IS
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45 | port (
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46 | a: IN std_logic_VECTOR(31 downto 0);
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47 | b: IN std_logic_VECTOR(31 downto 0);
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48 | clk: IN std_logic;
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49 | ce: IN std_logic;
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50 | result: OUT std_logic_VECTOR(31 downto 0));
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51 | END COMPONENT;
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52 | -----------------------------------------------------
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53 | COMPONENT sqrtFP IS
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54 | port (
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55 | a: IN std_logic_VECTOR(31 downto 0);
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56 | clk: IN std_logic;
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57 | ce: IN std_logic;
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58 | result: OUT std_logic_VECTOR(31 downto 0));
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59 | END COMPONENT;
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60 |
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61 | ----------------------------------------------------
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62 | COMPONENT mulFP IS
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63 | port (
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64 | a: IN std_logic_VECTOR(31 downto 0);
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65 | b: IN std_logic_VECTOR(31 downto 0);
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66 | clk: IN std_logic;
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67 | ce: IN std_logic;
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68 | result: OUT std_logic_VECTOR(31 downto 0));
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69 | END COMPONENT;
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70 | ------------------------------------
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71 | --If a greater then equal then true
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72 | COMPONENT compFP IS
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73 | port (
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74 | a: IN std_logic_VECTOR(31 downto 0);
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75 | b: IN std_logic_VECTOR(31 downto 0);
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76 | clk: IN std_logic;
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77 | ce: IN std_logic;
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78 | result: OUT std_logic_VECTOR(0 downto 0));
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79 | END COMPONENT;
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80 | --========================================================
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81 | CONSTANT PIdiv2 :std_logic_vector(31 DOWNTO 0):=X"3FC90FDB";--1.57079632679 PI/2 in FP Format
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82 | CONSTANT C0 :std_logic_vector(31 DOWNTO 0):=X"00000000";-- zahl 0 in FP format 32bit
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83 | CONSTANT C1 :std_logic_vector(31 DOWNTO 0):=X"3F800000";-- zahl 1 in FP format 32bit
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84 | CONSTANT C2 :std_logic_vector(31 DOWNTO 0):=X"40000000";-- zahl 2 in FP format 32bit
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85 | CONSTANT C05 :std_logic_vector(31 DOWNTO 0):=X"3F000000";-- zahl 0.5 in FP format 32bit
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86 | --==================================================================
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87 | SIGNAL ce1 :std_logic:= '0';
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88 | SIGNAL ce2 :std_logic:= '0';
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89 | SIGNAL ce3 :std_logic:= '0';
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90 | SIGNAL ce4 :std_logic:= '0';
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91 | SIGNAL ce5 :std_logic:= '0';
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92 | SIGNAL C1minX :std_logic_VECTOR(31 downto 0):=X"00000000";
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93 | SIGNAL Xinp2 :std_logic_VECTOR(31 downto 0):=X"00000000";
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94 | SIGNAL ainp05 :std_logic_VECTOR(0 downto 0):=(OTHERS => '0');-- output Compare Input(X) <= 0.5
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95 | SIGNAL mul2mX :std_logic_VECTOR(31 downto 0):=X"00000000";
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96 | SIGNAL C2powX :std_logic_VECTOR(31 downto 0):=X"00000000";
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97 | SIGNAL ain :std_logic_VECTOR(31 downto 0):=X"00000000";
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98 | SIGNAL sqrt2m :std_logic_VECTOR(31 downto 0):=X"00000000";
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99 | SIGNAL aou :std_logic_VECTOR(31 downto 0):=X"00000000";
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100 | SIGNAL Xq05 :std_logic_VECTOR(31 downto 0):=X"00000000";
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101 | SIGNAL Xk05 :std_logic_VECTOR(31 downto 0):=X"00000000";
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102 | SIGNAL angl1 :std_logic_VECTOR(31 downto 0):=X"00000000";
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103 | SIGNAL asinX :std_logic_VECTOR(31 downto 0):=X"00000000";
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104 | SIGNAL angl2 :std_logic_VECTOR(31 downto 0):=X"00000000";
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105 | SIGNAL state :INTEGER RANGE 0 TO 15:= 0;
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106 | --==================================================================
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107 | begin
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108 | --------------------------------------------------------------
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109 | pacos :PROCESS (clk)
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110 | VARIABLE cntrclk : INTEGER RANGE 0 TO 127:= 0;
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111 | --variable state :INTEGER RANGE 0 TO 7:= 0;
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112 | BEGIN
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113 | IF rising_edge(clk) THEN
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114 | IF nrst = '0' THEN
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115 | state <= 0;
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116 | cntrclk := 0;
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117 |
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118 | --(OTHERS => '0');
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119 |
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120 | ELSE
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121 | CASE state IS
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122 | WHEN 0 =>
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123 | IF ceacos = '1' THEN
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124 | ce1 <= '1';-- start für 1-x, x`2, ComP0.5
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125 | state <= 1;
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126 | ELSE
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127 | state <= 0;
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128 | END IF;
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129 | WHEN 1 => --- Ausführen 1-x,X`2,CompX
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130 | ce1 <= '0';
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131 | ce2 <= '1';-- start für mul2mxX,2powX berechnen
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132 | state <= 2;
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133 | WHEN 2 => ---- mul2mX,2powX fertig
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134 | ce2 <= '0';
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135 | state <= 3;
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136 | WHEN 3 =>
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137 | IF ainp05 = "1" THEN
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138 | ain <= C1minX;
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139 | ELSE
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140 | ain <= C2powX;
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141 | END IF;
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142 | cntrclk := 11;
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143 | ce3 <= '1'; --Start für afkt und sqrt
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144 | state <= 4;
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145 | WHEN 4 => -- ausführung afkt
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146 | IF cntrclk = 0 THEN -- dann afkt(x) fertig, sqrt sowieso
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147 | IF ainp05 = "1" THEN
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148 | Xq05 <= aou;
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149 | ELSE
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150 | Xk05 <= aou;
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151 | END IF;
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152 | ce4 <= '1';-- start für angl1,asinX
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153 | state <= 5;--
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154 | ELSE
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155 | ce3 <= '0';-- reset ce3
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156 | cntrclk := cntrclk - 1;
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157 | state <= 4;
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158 | END IF;
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159 | WHEN 5 => -- angl1 ,asinX fertig
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160 | ce4 <= '0';
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161 | ce5 <= '1';-- start für angl2
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162 | state <= 6;
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163 | WHEN 6 =>
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164 | ce5 <= '0'; --reset
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165 | state <= 7;
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166 | WHEN 7 =>
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167 | IF ainp05 = "1" THEN
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168 | acos <= angl1;
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169 | ELSE
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170 | acos <= angl2;
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171 | end IF;
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172 | state <= 0; --warten auf nächste Start
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173 | WHEN OTHERS =>
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174 | state <= 0;
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175 | END CASE;
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176 | END IF; -- if nrst/else
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177 | END IF; -- clk
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178 | END PROCESS;--end pacos
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179 |
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180 | --=======Implementation==================================
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181 |
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182 | Cafkt: afkt
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183 | generic map(P0=>X"3f7ffffd",-- +0.99999984852024669
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184 | P1=>X"be8c8cb6",-- -0.27451104135987186
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185 | P2=>X"00000000",-- +0.0
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186 | Q0=>X"3f800000",-- +1.0
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187 | Q1=>X"beb73881",-- -0.35785296234245088
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188 | Q2=>X"3c36a182"-- +0.011146905255803363
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189 | )
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190 | port map(nrst=>nrst,clk=>clk,ceafkt=>ce3,Xinp=>ain,aout=>aou);
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191 |
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192 | ---------------------------------------
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193 | cminX: subFP port map(a=>C1,b=>ainp,clk=>clk,ce=>ce1,result=>C1minX);
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194 | CmulX2: mulFP port map(a=>ainp,b=>ainp,clk=>clk,ce=>ce1,result=>Xinp2);
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195 | Ccomp: compFP port map(a=>ainp,b=>C05,clk=>clk,ce=>ce1,result=>ainp05);
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196 | --------
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197 | cmul2mX: mulFP port map(a=>C1minX,b=>C2,clk=>clk,ce=>ce2,result=>mul2mX);
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198 | Cmul2p: mulFP port map(a=>Xinp2,b=>C2,clk=>clk,ce=>ce2,result=>C2powX);
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199 | --------
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200 | csqrt2: sqrtFP port map(a=>mul2mX,clk=>clk,ce=>ce3,result=>sqrt2m);
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201 | ------
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202 | Cmula1: mulFP port map(a=>sqrt2m,b=>xq05,clk=>clk,ce=>ce4,result=>angl1);
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203 | Cmula2: mulFP port map(a=>Xk05,b=>ainp,clk=>clk,ce=>ce4,result=>asinX);
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204 | ------
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205 | csub5: subFP port map(a=>PIdiv2,b=>asinX,clk=>clk,ce=>ce5,result=>angl2);
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206 | ---------------------------------------------------
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207 | end Behavioral;
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