atanFP.vhd


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----------------------------------------------------------------------------------

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-- Company: 

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-- Engineer:a.Kurka 

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-- 

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-- Create Date:   06.06.2021 by a.kurka

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-- Design Name:  AS21

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-- Module Name:    atanFP - Behavioral 

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-- modified : 15.06.2021 by a.kurka 

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--Berechnet arctang aus Xin / Yin für Bereich -PI .... PI

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--    output Winkel in rad FP Format, benötigt 20 clk

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--    dauer 22 clk

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----------------------------------------------------------------------------------

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_ARITH.ALL;

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use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity atanFP is

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  port(  nrst      : in std_logic;

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      clk       : in std_logic;

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      ceatan     : in std_logic;-- startimpuls afkt

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      Xinp      :in std_logic_vector(31 downto 0);-- input X FP FP  format

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      Yinp      :in std_logic_vector(31 downto 0);-- input Y FP FP  format

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      atanFP    :OUT std_logic_vector(31 downto 0):=X"00000000"-- output Winkel(rad) in FP  format

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      );

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end atanFP;

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architecture Behavioral of atanFP is

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--=============================================

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COMPONENT afkt is

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  generic(  P0:std_logic_vector(31 downto 0):=X"00000000";

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        P1:std_logic_vector(31 downto 0):=X"00000000";

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        P2:std_logic_vector(31 downto 0):=X"00000000";

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        Q0:std_logic_vector(31 downto 0):=X"00000000";

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        Q1:std_logic_vector(31 downto 0):=X"00000000";

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        Q2:std_logic_vector(31 downto 0):=X"00000000"

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        );

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  port(  nrst      : in std_logic;

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      clk       : in std_logic;

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      ceafkt     : in std_logic;-- startimpuls afkt

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      Xinp      :in std_logic_vector(31 downto 0);--input afkt FP  format, immer positiv

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      aout    :OUT std_logic_vector(31 downto 0)-- output afkt FP  format

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      );

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END COMPONENT;

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------------------------------------------------------------

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COMPONENT mulFP IS

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  port (

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  a: IN std_logic_VECTOR(31 downto 0);

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  b: IN std_logic_VECTOR(31 downto 0);

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  clk: IN std_logic;

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  ce: IN std_logic;

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  result: OUT std_logic_VECTOR(31 downto 0));

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END COMPONENT;

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------------------------------------------------------------

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COMPONENT divFP IS

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  port (

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  a: IN std_logic_VECTOR(31 downto 0);

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  b: IN std_logic_VECTOR(31 downto 0);

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  clk: IN std_logic;

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  ce: IN std_logic;

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  result: OUT std_logic_VECTOR(31 downto 0)

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  );

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END COMPONENT;

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------------------------------------

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----if a >= b then result = 1

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--COMPONENT compFP IS

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--  port (

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--  a: IN std_logic_VECTOR(31 downto 0);

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--  b: IN std_logic_VECTOR(31 downto 0);

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--  clk: IN std_logic;

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--  ce: IN std_logic;

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--  result: OUT std_logic_VECTOR(0 downto 0));

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--END COMPONENT;

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-----------------------------------------------

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-- if a > b then result = "0001"

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COMPONENT cmpgr IS

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  PORT (

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    a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

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    b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

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    clk : IN STD_LOGIC;

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    ce : IN STD_LOGIC;

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    result : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)

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  );

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END COMPONENT;-- cmpgr;

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-----------------------------------------

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COMPONENT subFP IS

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  port (

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  a: IN std_logic_VECTOR(31 downto 0);

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  b: IN std_logic_VECTOR(31 downto 0);

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  clk: IN std_logic;

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  ce: IN std_logic;

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  result: OUT std_logic_VECTOR(31 downto 0));

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END COMPONENT;

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---------------------------------------------

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COMPONENT addFP IS

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  port (

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  a: IN std_logic_VECTOR(31 downto 0);

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  b: IN std_logic_VECTOR(31 downto 0);

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  clk: IN std_logic;

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  ce: IN std_logic;

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  result: OUT std_logic_VECTOR(31 downto 0));

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END COMPONENT;

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--=======================================================

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--==================== Signale für afkt ==================================

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CONSTANT PIdiv2   :std_logic_vector(31 DOWNTO 0):=X"3FC90FDB";--1.57079632679 PI/2=+90 deg

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CONSTANT PIndiv2   :std_logic_vector(31 DOWNTO 0):=X"BFC90FDB";--1.57079632679 -PI/2=-90 deg

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CONSTANT PI     :std_logic_vector(31 DOWNTO 0):=X"40490FDB";-- +3.14159265359-- PI=180 deg

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CONSTANT PIn     :std_logic_vector(31 DOWNTO 0):=X"C0490FDB";--  -3.14159265359-- PI=-180 deg

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CONSTANT PIn135     :std_logic_vector(31 DOWNTO 0):=X"C016CBE4";--  -2.35619449019-- -135 deg

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CONSTANT PI135     :std_logic_vector(31 DOWNTO 0):=X"4016CBE4";--  +2.35619449019-- +135 deg

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-----------------------------------------------

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SIGNAL stateatan  :integer range 0 to 15:= 0;

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--SIGNAL ceatan extern

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SIGNAL cecomp     :std_logic:= '0';

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SIGNAL fYgr       :std_logic_vector(0 DOWNTO 0):=(OTHERS => '0');--if Y(a)>X(b) then := '1'

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SIGNAL Yneg    :std_logic:='0';-- flag Y negativ  = 1

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SIGNAL Xneg    :std_logic:='0';-- flag X negativ  = 1

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SIGNAL Yabs    :std_logic_vector(31 DOWNTO 0):=X"00000000";-- Abs Input Yinp

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SIGNAL Xabs    :std_logic_vector(31 DOWNTO 0):=X"00000000";-- Abs Input Xinp

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SIGNAL adiv    :std_logic_VECTOR(31 downto 0):=X"00000000";

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SIGNAL bdiv    :std_logic_VECTOR(31 downto 0):=X"00000000";

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SIGNAL ainp    :std_logic_VECTOR(31 downto 0):=X"00000000";-- inputs für Addition/subtraktion

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SIGNAL binp    :std_logic_VECTOR(31 downto 0):=X"00000000";--inputs für Addition/subtraktion

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SIGNAL cediv   :std_logic:= '0';

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signal resdiv  :std_logic_VECTOR(31 downto 0):=X"00000000";-- resutat a/b

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SIGNAL ce1      :std_logic:='0';-- Start resdiv^2

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--

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SIGNAL ain    :std_logic_VECTOR(31 downto 0):=X"00000000";-- resultat resdiv^2= input afkt

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SIGNAL ce2     :std_logic:= '0'; -- start afkt

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SIGNAL aou    :std_logic_VECTOR(31 downto 0):=X"00000000";--resultaat afkt(resdiv^2)

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---

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SIGNAL ce3       :std_logic:= '0';-- start atang = aou* ainp

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SIGNAL atang     :std_logic_VECTOR(31 downto 0):=X"00000000";--resultat  atang[-1,1]

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-----------

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SIGNAL ceadd     :std_logic:= '0';  -- start add

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SIGNAL cesub     :std_logic:= '0';  -- start sub

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SIGNAL atanFPa    :std_logic_VECTOR(31 downto 0):=X"00000000";-- resultat nach addition

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SIGNAL atanFPs    :std_logic_VECTOR(31 downto 0):=X"00000000";-- resultat nach substraction

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-- atanFP resultat ----

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--==================================================================

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BEGIN

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--------------------------------------------------------------

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patan :PROCESS (clk)

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VARIABLE cntrclk : INTEGER RANGE 0 TO 127:= 0;

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--variable state :INTEGER RANGE 0 TO 15:= 0;

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variable sign :std_logic_vector(1 DOWNTO 0):= "00";--Yneg(1),Xneg(0)

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BEGIN

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  IF rising_edge(clk) THEN

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    IF nrst = '0' THEN

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      stateatan <= 0;

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      cntrclk := 0;

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      cecomp <= '0';

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      sign := "00";

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      --(OTHERS => '0');

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    ELSE

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      CASE stateatan IS

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        WHEN 0 =>

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          IF ceatan = '1' THEN

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            IF (Yinp = X"00000000") AND (Xinp = X"00000000")  THEN

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              atanFP <= X"00000000";

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              stateatan <= 0;-- ungültige wert

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            ELSE

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              stateatan <= 1;

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            END IF;

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          ELSE

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            stateatan <= 0;

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          END IF;

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        WHEN 1 => ---testen Yinp

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            IF Yinp(31) = '1' THEN -- if negativ

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              Yabs <= Yinp AND X"7FFFFFFF";

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              sign(1) := '1';-- Y negativ

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            ELSE

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              Yabs <= Yinp;

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              sign(1) := '0';-- Y positiv

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            END IF;

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            IF Xinp(31) = '1' THEN -- if negativ

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              Xabs <= Xinp AND X"7FFFFFFF";

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              sign(0) := '1'; -- X negativ

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            ELSE

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              Xabs <= Xinp;

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              sign(0) := '0'; -- X positi

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            END IF;

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            cecomp <= '1';-- start für comp Xabs >= Yabs

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            stateatan <= 2;

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        WHEN 2 =>

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            cecomp <= '0';-- reset

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            stateatan <= 3;

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        WHEN 3 =>  --cmpgr if (a)Yabs > (b)Xabs th

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            -- oktanten 2,3,6, 7

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            IF  fYgr = "0001" THEN -- if Yabs > Xabs :

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              adiv <= Xabs;-- Inputs vertauschen

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              bdiv <= Yabs;

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            ELSE  -- Yabs <= Xabs,Oktant 1,4,5,8

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              adiv <= Yabs;

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              bdiv <= Xabs;

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            END IF;

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            cntrclk := 1;

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            cediv <= '1';-- div starten

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            stateatan <= 4;

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        WHEN 4 =>  -- div ausführen

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          IF cntrclk > 0 THEN

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            cntrclk := cntrclk -1;

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            cediv <= '0';-- reset

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            stateatan <= 4;

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          ELSE

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            ce1 <= '1';-- star für x^2 

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            stateatan <= 5;

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          END IF;

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        WHEN 5 =>  -- sq(x) cinpsq ausführen

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            ce1 <= '0';

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            ce2 <= '1';-- start für afkt

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            cntrclk := 11;

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            stateatan <= 6;

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        WHEN 6 => ---- afkt ausführen

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          IF cntrclk = 0 THEN

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            ce3 <= '1';-- aou * resdiv starten

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            stateatan <= 7;--afkt fertig

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          ELSE

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            ce2 <= '0'; --reset

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            cntrclk := cntrclk -1;

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            stateatan <= 6;

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          END IF;

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        WHEN 7 =>  --aou * ainp=resdiv ausführen, atang[0,1] fertig

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          ce3 <= '0';-- reset

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          stateatan <= 8;

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        WHEN 8 =>

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          binp <= atang;-- resultat arctang[0,1]

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          IF  fYgr = "0001" THEN -- if Yabs > Xabs :,Okt=2

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            IF sign = "00" THEN -- oktant 2: 90grd - resdiv

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              ainp <= PIdiv2;--start 90gr - resdiv

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              stateatan <= 12;-- zu sub

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            ELSIF sign = "01" THEN -- oktant 3:90grd + resdiv

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                ainp <= PIdiv2;--

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                stateatan <= 9;-- zu add

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                -------

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            ELSIF sign = "10" THEN -- oktant 7:270Grd + resdiv

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                ainp <= PIndiv2;--start -90grd + resdiv

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                stateatan <= 9;

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            ELSE ---------sign = "11" THEN -- oktant6

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                ainp <= PIndiv2;--start -90grd - resdiv

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                stateatan <= 12;

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            END IF;

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          ELSE -- Yabs >= Xabs, 

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            IF sign = "00" THEN -- oktant 1

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                ainp <= X"00000000";-- ohne aenderung

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                stateatan <= 9;

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            ELSIF sign = "01" THEN --oktant 4: 180grd - resdiv

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                ainp <= PI;--start 180grd - resdiv

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                stateatan <= 12;

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                -------

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            ELSIF sign = "10" THEN -- oktant 8

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                ainp <= X"00000000";----start 0 grd - resdiv

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                stateatan <= 12;

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            ELSE ----- sign = "11" THEN -- oktant5

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                ainp <= PIn;----start -180grd + resdiv

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                stateatan <= 9;

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            END IF;

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          END IF;

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          --------------------------------

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        WHEN 9 =>  -- adition ausführen    

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            ceadd <= '1';-- start add

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            --atanFP <= atanFPa;-- resultat speichern

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            stateatan <= 10;--warten auf nächste Start

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        WHEN 10 =>

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            ceadd <= '0';-- reset

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            --atanFP <= atanFPa;-- resultat speichern

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            stateatan <= 11;--warten auf nächste Start

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        WHEN 11 =>

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            atanFP <= atanFPa;-- resultat speichern

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            stateatan <= 0;

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            ------------------------------

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        WHEN 12 => -- subtraktion ausführen

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            cesub <= '1';-- start sub

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            --atanFP <= atanFPs;-- resultat speichern

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            stateatan <= 13; --warten auf nächste Start

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        WHEN 13 => 

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            cesub <= '0';-- reset

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            --atanFP <= atanFPs;-- resultat speichern

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            stateatan <= 14; --

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        WHEN 14 =>

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            atanFP <= atanFPs;-- resultat speichern

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            stateatan <= 0; --warten auf nächste Start

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            ---------------------------------

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        WHEN OTHERS =>

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          stateatan <= 0;

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      END CASE;

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    END IF; -- if nrst/else

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  END IF; -- clk

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END PROCESS;--end pacos

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--=======Implementation==================================

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--  Werte aus cfunctg-------------------------

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--X"40b5aa96",--P0  +5.67707365457  index 0

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--X"40723f49",--P1  +3.78511273085

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--X"3e76b19e",--P2  +0.240911935532 index 2

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--X"00000000"             

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--X"40b5aa9c",--Q0  +5.67707629595 index 0

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--X"40b5ac55",--Q1  +5.6772864448

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--X"3f800000",--Q2  +1.0         indesx 2

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--X"00000000"

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Cafkt:   afkt

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    generic map(P0=>X"40b5aa96",-- +5.67707365457  index 0 

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            P1=>X"40723f49",-- +3.78511273085

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            P2=>X"3e76b19e",-- +0.240911935532 index 2  

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            Q0=>X"40b5aa9c",-- +5.67707629595 index 0 

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            Q1=>X"40b5ac55",-- +5.6772864448

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            Q2=>X"3f800000"--  +1.0       indesx 2 

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            )   

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              port map(nrst=>nrst,clk=>clk,ceafkt=>ce2,Xinp=>ain,aout=>aou);

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--cfunctg: func_atg   port map(nrst=>nrst,clk=>clk,cefkt=>ce2,Xinp=>ain,aout=>aou);-- abgeschaltet

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ccomp: cmpgr port map(a=>Yabs,b=>Xabs,clk=>clk,ce=>cecomp,result=>fYgr);

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cdiv:  divFP port map(a=>adiv,b=>bdiv,clk=>clk,ce=>cediv,result=>resdiv);  

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cinpsq:  mulFP port map(a=>resdiv,b=>resdiv,clk=>clk,ce=>ce1,result=>ain);

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cfuncmul: mulFP port map(a=>resdiv,b=>aou,clk=>clk,ce=>ce3,result=>atang);

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cadd:  addFP port map(a=>ainp,b=>binp,clk=>clk,ce=>ceadd,result=> atanFPa);

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csub:  subFP port map(a=>ainp,b=>binp,clk=>clk,ce=>cesub,result=> atanFPs);

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---------------------------------------------------  

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END Behavioral;