CosFP.vhd

----------------------------------------------------------------------------------

-- Company:Zuritronic 

-- Engineer:a.Kurka 

--

-- Create Date:   06.05.2021 by a.kurka

-- Design Name:     AS21

-- Module Name:    cosFP - Behavioral 

--  modified : 09.05.2021 by a.kurka

-- cos = func_C(ainp^2); -- für den Bereich [-PI/2,PI/2]

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CosFP is

  port(  nrst      : in std_logic;

      clk       : in std_logic;

      cecos     : in std_logic;-- startimpuls afkt

      ainp      :in std_logic_vector(31 downto 0);-- input afkt FP  format

      cos      :OUT std_logic_vector(31 downto 0)-- output afkt FP  format

      );

end CosFP;

architecture Behavioral of CosFP is

--====================================================

COMPONENT func_C is

  port(  nrst      : in std_logic;

      clk       : in std_logic;

      cefktC     : in std_logic;-- startimpuls fkt_C

      Xinp      :in std_logic_vector(31 downto 0);-- input afkt FP  format

      aout    :OUT std_logic_vector(31 downto 0)-- output afkt FP  format

      );

END COMPONENT;

-----------------------------------------

COMPONENT mulFP IS

  port (

  a: IN std_logic_VECTOR(31 downto 0);

  b: IN std_logic_VECTOR(31 downto 0);

  clk: IN std_logic;

  ce: IN std_logic;

  result: OUT std_logic_VECTOR(31 downto 0));

END COMPONENT;

--========================================================

CONSTANT PIdiv2   :std_logic_vector(31 DOWNTO 0):=X"3FC90FDB";--1.57079632679 PI/2 in FP Format

--==================================================================

SIGNAL ce1     :std_logic:= '0';

SIGNAL ce2     :std_logic:= '0';

SIGNAL ain    :std_logic_VECTOR(31 downto 0):=X"00000000";

--==================================================================

begin

--------------------------------------------------------------

pcos :PROCESS (clk)

VARIABLE cntrclk : INTEGER RANGE 0 TO 127:= 0;

variable state :INTEGER RANGE 0 TO 7:= 0;

BEGIN

  IF rising_edge(clk) THEN

    IF nrst = '0' THEN

      state := 0;

      cntrclk := 0;

      --(OTHERS => '0');

    ELSE

      CASE state IS

        WHEN 0 =>

          IF cecos = '1' THEN

            ce1 <= '1';-- start für 1-x, x`2, ComP0.5

            state := 1;

          ELSE

            state := 0;

          END IF;

        WHEN 1 => --- Ausführen ain :=ainp^2

            ce1 <= '0';

            ce2 <= '1';-- start für fkt_c

            cntrclk := 11;

            state := 2;

        WHEN 2 => ---- mul2mX,2powX fertig

          IF cntrclk = 0 THEN

            state := 0;--warten auf nächste Start

          ELSE

            ce2 <= '0';

            cntrclk := cntrclk -1;

            state := 2;

          END IF;

        WHEN OTHERS =>

          state := 0;

      END CASE;

    END IF; -- if nrst/else

  END IF; -- clk

END PROCESS;--end pacos

--=======Implementation==================================

cmulX : mulFP port map(a=>ainp,b=>ainp,clk=>clk,ce=>ce1,result=>ain);

cfuncC: func_c port map(nrst=>nrst,clk=>clk,cefktC=>ce2,Xinp=>ain,aout=>cos);

---------------------------------------------------  

end Behavioral;