1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.all;
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3 |
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4 | entity ITPModul_tb is
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5 | end entity ITPModul_tb;
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6 |
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7 | architecture testbench of ITPModul_tb is
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8 |
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9 | constant clk_frequency : integer := 100_000_000;
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10 | constant clk_period : time := 1 sec / clk_frequency;
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11 | signal simulation_run : boolean := true;
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12 |
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13 | signal tb_nrst : std_logic := '0';
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14 | signal tb_clk : std_logic := '0';
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15 | signal tb_XS : std_logic_vector(31 downto 0) := (others => '1'); -- Startpunkt Koordinate X
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16 | signal tb_YS : std_logic_vector(31 downto 0) := (others => '1'); -- Startpunkt Koordinate Y
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17 | signal tb_ZS : std_logic_vector(31 downto 0) := (others => '1'); -- Startpunkt Koordinate Z
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18 | signal tb_XT : std_logic_vector(31 downto 0) := (others => '1'); -- Koordinate X relativ (XE-XS)
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19 | signal tb_YT : std_logic_vector(31 downto 0) := (others => '1'); -- Koordinate Y relativ (YE-YS)
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20 | signal tb_ZT : std_logic_vector(31 downto 0) := (others => '1'); -- Koordinate Z relativ (ZE-ZS)
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21 | signal tb_pfrq : std_logic_vector(23 downto 0) := (others => '1'); --Bahn-Periode in anzahl CLK
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22 | signal tb_L1 : std_logic_vector(15 downto 0) := (others => '1'); -- länge Arm1 in mm
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23 | signal tb_L2 : std_logic_vector(15 downto 0) := (others => '1'); -- länge Arm2 in mm
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24 | signal tb_L3 : std_logic_vector(15 downto 0) := (others => '1'); -- länge Arm3 in mm
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25 | -----------------------
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26 | signal tb_Xlin : std_logic_vector(15 downto 0) := (others => '1'); -- Koord LinStz
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27 | signal tb_Ylin : std_logic_vector(15 downto 0) := (others => '1'); -- Max.Eingabe +/-327.67
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28 | signal tb_ebene : std_logic_vector(3 downto 0) := (others => '1'); --interpolationsebene für LinSatz
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29 | signal tb_Xactiv : std_logic := '0';
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30 | signal tb_Yactiv : std_logic := '0';
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31 | signal tb_celin : std_logic := '0'; ---start interpolation für linstz in einer ebene
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32 | ----------------------------------------
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33 | signal tb_stopp : std_logic := '0'; -- stop interpolation,(stopp+) nach Endlage
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34 | signal tb_RampRun : std_logic := '0'; -- rampe aktiv =1
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35 | signal tb_strimp : std_logic := '0'; -- start interpolation
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36 | signal tb_ce : std_logic := '0'; -- start interpolation von kreis oder XYZ Satz : InversTransf
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37 | -------------------------------
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38 | signal tb_calcok : std_logic := '0'; -- signalisiert alle berechnungen sind fertig
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39 | signal tb_XAout : std_logic_vector(31 downto 0) := X"00000000"; --virtuelle aktuelle koordinate
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40 | signal tb_YAout : std_logic_vector(31 downto 0) := X"00000000";
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41 | signal tb_ZAout : std_logic_vector(31 downto 0) := X"00000000";
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42 | signal tb_ITPmod : std_logic_vector(2 downto 0) := "000"; --ITP für Status Meldung an CPU
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43 | signal tb_oAXdif : std_logic_vector(95 downto 0) := (others => '0'); --Sollwertdiff(16Bit) von inv.Transfer und Lin
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44 | signal tb_oImpLk : std_logic := '1'; --impulse von xyz itp
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45 | signal tb_enditp : std_logic := '0'; -- ende von Kontur:=0 (enditp-)
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46 | signal tb_itprun : std_logic := '0'; -- =1:interpolator läuft,aktuelle Sollwerte in oAXinkr(6x 32bit)
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47 | signal tb_testdata : std_logic_vector(15 downto 0) := X"0000";
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48 |
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49 |
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50 | begin
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51 |
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52 | tb_nrst <= '0', '1' after 10 * clk_period;
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53 | tb_clk <= not tb_clk after clk_period / 2 when simulation_run;
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54 |
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55 |
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56 | main: process
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57 | begin
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58 | wait for 10 us;
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59 | simulation_run <= false;
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60 | wait;
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61 | end process;
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62 |
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63 | dut: entity work.ITPModul
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64 | port map
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65 | (
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66 | nrst => tb_nrst, -- : in std_logic;
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67 | clk => tb_clk, -- : in std_logic;
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68 | XS => tb_XS, -- : in std_logic_vector(31 downto 0); -- Startpunkt Koordinate X
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69 | YS => tb_YS, -- : in std_logic_vector(31 downto 0); -- Startpunkt Koordinate Y
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70 | ZS => tb_ZS, -- : in std_logic_vector(31 downto 0); -- Startpunkt Koordinate Z
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71 | XT => tb_XT, -- : in std_logic_vector(31 downto 0); -- Koordinate X relativ (XE-XS)
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72 | YT => tb_YT, -- : in std_logic_vector(31 downto 0); -- Koordinate Y relativ (YE-YS)
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73 | ZT => tb_ZT, -- : in std_logic_vector(31 downto 0); -- Koordinate Z relativ (ZE-ZS)
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74 | pfrq => tb_pfrq, -- : in std_logic_vector(23 downto 0); --Bahn-Periode in anzahl CLK
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75 | L1 => tb_L1, -- : in std_logic_vector(15 downto 0); -- länge Arm1 in mm
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76 | L2 => tb_L2, -- : in std_logic_vector(15 downto 0); -- länge Arm2 in mm
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77 | L3 => tb_L3, -- : in std_logic_vector(15 downto 0); -- länge Arm3 in mm
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78 | ----------------------------------
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79 | Xlin => tb_Xlin, -- : in std_logic_vector(15 downto 0); -- Koord LinStz
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80 | Ylin => tb_Ylin, -- : in std_logic_vector(15 downto 0); -- Max.Eingabe +/-327.67
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81 | ebene => tb_ebene, -- : in std_logic_vector(3 downto 0); --interpolationsebene für LinSatz
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82 | Xactiv => tb_Xactiv, -- : in std_logic;
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83 | Yactiv => tb_Yactiv, -- : in std_logic;
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84 | celin => tb_celin, -- : in std_logic; ---start interpolation für linstz in einer ebene
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85 | ---------------------------------------------------
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86 | stopp => tb_stopp, -- : in std_logic; -- stop interpolation,(stopp+) nach Endlage
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87 | RampRun => tb_RampRun, -- : in std_logic; -- rampe aktiv =1
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88 | strimp => tb_strimp, -- : in std_logic; -- start interpolation
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89 | ce => tb_ce, -- : in std_logic; -- start interpolation von kreis oder XYZ Satz : InversTransf
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90 | ------------------------------------------
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91 | calcok => tb_calcok, -- : out std_logic := '0'; -- signalisiert alle berechnungen sind fertig
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92 | XAout => tb_XAout, -- : out std_logic_vector(31 downto 0) := X"00000000"; --virtuelle aktuelle koordinate
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93 | YAout => tb_YAout, -- : out std_logic_vector(31 downto 0) := X"00000000";
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94 | ZAout => tb_ZAout, -- : out std_logic_vector(31 downto 0) := X"00000000";
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95 | ITPmod => tb_ITPmod, -- : out std_logic_vector(2 downto 0) := "000"; --ITP für Status Meldung an CPU
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96 | oAXdif => tb_oAXdif, -- : out std_logic_vector(95 downto 0) := (others => '0'); --Sollwertdiff(16Bit) von inv.Transfer und Lin
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97 | oImpLk => tb_oImpLk, -- : out std_logic := '1'; --impulse von xyz itp
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98 | enditp => tb_enditp, -- : out std_logic := '0'; -- ende von Kontur:=0 (enditp-)
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99 | itprun => tb_itprun, -- : out std_logic := '0'; -- =1:interpolator läuft,aktuelle Sollwerte in oAXinkr(6x 32bit)
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100 | testdata => tb_testdata -- : out std_logic_vector(15 downto 0) := X"0000"
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101 | );
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102 |
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103 | end architecture testbench;
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