arctanFP.vhd

----------------------------------------------------------------------------------

-- test mulFP1

-- Company:ak development GmbH 

-- Engineer:a.Kurka, 31.8.2024 

-- www.akdevelopment.ch

-- ursprüngliche ArcTang Berechnung geändert

-- zu Testprogramm, so konnte man das bestehende Testbench verwenden

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- synthesis translate_off

LIBRARY XilinxCoreLib;

-- synthesis translate_on

entity arctanFP is

  port(  nrst      : in std_logic;

      clk       : in std_logic;

      ceatan     : in std_logic;-- startimpuls afkt

      Xinp      :in std_logic_vector(31 downto 0);-- input X FP FP  format

      Yinp      :in std_logic_vector(31 downto 0);-- input Y FP FP  format

      outvalid    :OUT std_logic:= '0';

      atanFPo  :OUT std_logic_vector(31 downto 0):=X"00000000"  -- output Winkel(rad) in FP  format

      );

end arctanFP;

architecture Behavioral of arctanFP is

------------------------------------------------------------

--- IP coregen 5.0----------------------

--COMPONENT mulFP IS

--  port (

--  a: IN std_logic_VECTOR(31 downto 0);

--  b: IN std_logic_VECTOR(31 downto 0);

--  clk: IN std_logic;

--  ce: IN std_logic;

--  result: OUT std_logic_VECTOR(31 downto 0)

--  );

--END COMPONENT;

------------------------------------------------

-----IP coregen 6.1--------------------

COMPONENT  mulFP1 IS

  PORT (

    aclk : IN STD_LOGIC;

    s_axis_a_tvalid : IN STD_LOGIC;

    s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    s_axis_b_tvalid : IN STD_LOGIC;

    s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    m_axis_result_tvalid : OUT STD_LOGIC;

    m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)

  );

END COMPONENT  ;

-----------------------------------------------

SIGNAL resvalid :std_logic;

-----------------------------------------------

SIGNAL stateatan  :integer range 0 to 7:= 0;

--SIGNAL InpA      :std_logic_VECTOR(31 downto 0):= (OTHERS => '0');

--SIGNAL InpB      :std_logic_VECTOR(31 downto 0):= (OTHERS => '0');

--SIGNAL TestOutp  :std_logic_VECTOR(31 downto 0);---:= (OTHERS => '0');

SIGNAL ce1      :std_logic:='0';-- Start resdiv^2

--

--==================================================================

BEGIN

--------------------------------------------------------------

patan :PROCESS (clk)

VARIABLE cntrclk : INTEGER RANGE 0 TO 3:= 0;

BEGIN

  IF rising_edge(clk) THEN

    IF nrst = '0' THEN

      stateatan <= 0;

      ce1 <= '0';

      --InpA <= (OTHERS => '0');

      ---InpB <= (OTHERS => '0');

      cntrclk := 0;

      --(OTHERS => '0');

    ELSE

      CASE stateatan IS

        WHEN 0 =>

          IF ceatan = '1' THEN

              stateatan <= 1;

              --InpA <= Xinp;

              --InpB <= Yinp;

              cntrclk := 1;-- time for calculation

          ELSE

            stateatan <= 0;

          END IF;

        WHEN 1 =>  

          ce1 <= '1'; -- start for MUL Xinp * Yinp

          stateatan <= 2;

        WHEN 2 => ---test Xinp * Yinp

          IF cntrclk > 0 THEN  -- wait for calculation

            cntrclk := cntrclk - 1;

            stateatan <= 2;

          ELSE

            ce1 <= '0'; -- reset

            stateatan <= 3;-- 

          END IF;

        WHEN 3 =>

            outvalid <= resvalid;

            --atanFPo <= TestOutp;

            stateatan <= 0;--mul result ready ?

        WHEN OTHERS =>

          stateatan <= 0;

      END CASE;

    END IF; -- if nrst/else

  END IF; -- clk

END PROCESS;--end pacos

-- Implementation: Mul FP test

-- Latency = 1

---cfuncmul: mulFP port map(a=>InpA,b=>InpB,clk=>clk,ce=>ce1,result=>TestOutp);

-----------------------------------------------

--SIGNAL resvalid :std_logic;

----------------erste test; mit Internen Signalen---------------------------------

--cmulFP1 :mulFP1 port map (

--    aclk => clk,          ---: IN STD_LOGIC;

--    s_axis_a_tvalid => ce1,  ---: IN STD_LOGIC;

--    s_axis_a_tdata => InpA,  --- : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

--    s_axis_b_tvalid=> ce1,    --- : IN STD_LOGIC;

--    s_axis_b_tdata => InpB,  --- : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

--    m_axis_result_tvalid => resvalid,  ---    : OUT STD_LOGIC;

--    m_axis_result_tdata => TestOutp   ----: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)

--    );

-------------zweite test : Direkt auf Entity I/O a------------------------------

cmulFP1 :mulFP1 port map (

    aclk => clk,          ---: IN STD_LOGIC;

    s_axis_a_tvalid => ce1,  ---: IN STD_LOGIC;

    s_axis_a_tdata => Xinp,  --- : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    s_axis_b_tvalid=> ce1,    --- : IN STD_LOGIC;

    s_axis_b_tdata => Yinp,  --- : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    m_axis_result_tvalid => resvalid,  ---    : OUT STD_LOGIC;

    m_axis_result_tdata => atanFPo    ----: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)

    );

---------------------------------------------------  

END Behavioral;