arctanFP.vhd

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-- test mulFP1

-- Company:ak development GmbH 

-- Engineer:a.Kurka, 31.8.2024 

-- www.akdevelopment.ch

-- ursprüngliche ArcTang Berechnung geändert

-- zu Testprogramm, so konnte man das bestehende Testbench verwenden

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- synthesis translate_off

LIBRARY XilinxCoreLib;

-- synthesis translate_on

entity arctanFP is

  port(  nrst      : in std_logic;

      clk       : in std_logic;

      ceatan     : in std_logic;-- startimpuls afkt

      Xinp      :in std_logic_vector(31 downto 0);-- input X FP FP  format

      Yinp      :in std_logic_vector(31 downto 0);-- input Y FP FP  format

      atanFPo  :OUT std_logic_vector(31 downto 0):=X"00000000"  -- output Winkel(rad) in FP  format

      );

end arctanFP;

architecture Behavioral of arctanFP is

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COMPONENT mulFP

  port (

   a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    operation_nd : IN STD_LOGIC;

    clk : IN STD_LOGIC;

    ce : IN STD_LOGIC;

    result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

    rdy : OUT STD_LOGIC

  );

END COMPONENT;

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SIGNAL stateatan  :integer range 0 to 7:= 0;

SIGNAL InpA      :std_logic_VECTOR(31 downto 0):= (OTHERS => '0');

SIGNAL InpB      :std_logic_VECTOR(31 downto 0):= (OTHERS => '0');

SIGNAL TestOutp  :std_logic_VECTOR(31 downto 0);----:= (OTHERS => '0');

SIGNAL ce1      :std_logic:='0';--

SIGNAL nd      :std_logic:='0';--

SIGNAL outrdy      :std_logic;--

--

--==================================================================

BEGIN

--------------------------------------------------------------

patan :PROCESS (clk)

BEGIN

  IF rising_edge(clk) THEN

    IF nrst = '0' THEN

      stateatan <= 0;

      ce1 <= '0';

      nd <= '0';

      InpA <= (OTHERS => '0');

      InpB <= (OTHERS => '0');

      atanFPo <= (OTHERS => '0');

      --TestOutp <= (OTHERS => '0');

      --(OTHERS => '0');

    ELSE

      CASE stateatan IS

        WHEN 0 =>

          IF ceatan = '1' THEN

              InpA <= Xinp;

              InpB <= Yinp;

              ce1 <= '1'; -- clk on

              stateatan <= 1;

          ELSE

            stateatan <= 0;

          END IF;

        WHEN 1 =>  

          nd <= '1'; -- new data,start for MUL Xinp * Yinp

          stateatan <= 2;

        WHEN 2 => ---wait for result Xinp * Yinp

          IF outrdy = '1' THEN

            atanFPo <= TestOutp;--mul result ready

            stateatan <= 3;

          ELSE

            nd <= '0'; -- reset

            stateatan <= 2;-- 

          END IF;

        WHEN 3 =>

            ce1 <= '0';

            stateatan <= 0;--wait for next start

        WHEN OTHERS =>

          stateatan <= 0;

      END CASE;

    END IF; -- if nrst/else

  END IF; -- clk

END PROCESS;--end pacos

-- Implementation: Mul FP test

-- Latency = 8

cfuncmul: mulFP port map(a=>InpA,b=>InpB,operation_nd=>nd,clk=>clk,ce=>ce1,result=>Testoutp,rdy=>outrdy);

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END Behavioral;