mulFP.vhd

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-- You must compile the wrapper file mulFP.vhd when simulating

-- the core, mulFP. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified

-- below are supported by Xilinx, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- synthesis translate_off

LIBRARY XilinxCoreLib;

-- synthesis translate_on

ENTITY mulFP IS

  PORT (

    a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    operation_nd : IN STD_LOGIC;

    clk : IN STD_LOGIC;

    ce : IN STD_LOGIC;

    result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

    rdy : OUT STD_LOGIC

  );

END mulFP;

ARCHITECTURE mulFP_a OF mulFP IS

-- synthesis translate_off

COMPONENT wrapped_mulFP

  PORT (

    a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    operation_nd : IN STD_LOGIC;

    clk : IN STD_LOGIC;

    ce : IN STD_LOGIC;

    result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

    rdy : OUT STD_LOGIC

  );

END COMPONENT;

-- Configuration specification

  FOR ALL : wrapped_mulFP USE ENTITY XilinxCoreLib.floating_point_v5_0(behavioral)

    GENERIC MAP (

      c_a_fraction_width => 24,

      c_a_width => 32,

      c_b_fraction_width => 24,

      c_b_width => 32,

      c_compare_operation => 8,

      c_has_a_nd => 0,

      c_has_a_negate => 0,

      c_has_a_rfd => 0,

      c_has_aclr => 0,

      c_has_add => 0,

      c_has_b_nd => 0,

      c_has_b_negate => 0,

      c_has_b_rfd => 0,

      c_has_ce => 1,

      c_has_compare => 0,

      c_has_cts => 0,

      c_has_divide => 0,

      c_has_divide_by_zero => 0,

      c_has_exception => 0,

      c_has_fix_to_flt => 0,

      c_has_flt_to_fix => 0,

      c_has_flt_to_flt => 0,

      c_has_inexact => 0,

      c_has_invalid_op => 0,

      c_has_multiply => 1,

      c_has_operation_nd => 1,

      c_has_operation_rfd => 0,

      c_has_overflow => 0,

      c_has_rdy => 1,

      c_has_sclr => 0,

      c_has_sqrt => 0,

      c_has_status => 0,

      c_has_subtract => 0,

      c_has_underflow => 0,

      c_latency => 8,

      c_mult_usage => 0,

      c_optimization => 1,

      c_rate => 1,

      c_result_fraction_width => 24,

      c_result_width => 32,

      c_speed => 2,

      c_status_early => 0,

      c_xdevicefamily => "aartix7"

    );

-- synthesis translate_on

BEGIN

-- synthesis translate_off

U0 : wrapped_mulFP

  PORT MAP (

    a => a,

    b => b,

    operation_nd => operation_nd,

    clk => clk,

    ce => ce,

    result => result,

    rdy => rdy

  );

-- synthesis translate_on

END mulFP_a;