mulFP1.vhd

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-- You must compile the wrapper file mulFP1.vhd when simulating

-- the core, mulFP1. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified

-- below are supported by Xilinx, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- synthesis translate_off

LIBRARY XilinxCoreLib;

-- synthesis translate_on

ENTITY mulFP1 IS

  PORT (

    aclk : IN STD_LOGIC;

    s_axis_a_tvalid : IN STD_LOGIC;

    s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    s_axis_b_tvalid : IN STD_LOGIC;

    s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    m_axis_result_tvalid : OUT STD_LOGIC;

    m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)

  );

END mulFP1;

ARCHITECTURE mulFP1_a OF mulFP1 IS

-- synthesis translate_off

COMPONENT wrapped_mulFP1

  PORT (

    aclk : IN STD_LOGIC;

    s_axis_a_tvalid : IN STD_LOGIC;

    s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    s_axis_b_tvalid : IN STD_LOGIC;

    s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    m_axis_result_tvalid : OUT STD_LOGIC;

    m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)

  );

END COMPONENT;

-- Configuration specification

  FOR ALL : wrapped_mulFP1 USE ENTITY XilinxCoreLib.floating_point_v6_1(behavioral)

    GENERIC MAP (

      C_A_FRACTION_WIDTH => 24,

      C_A_TDATA_WIDTH => 32,

      C_A_TUSER_WIDTH => 1,

      C_A_WIDTH => 32,

      C_B_FRACTION_WIDTH => 24,

      C_B_TDATA_WIDTH => 32,

      C_B_TUSER_WIDTH => 1,

      C_B_WIDTH => 32,

      C_COMPARE_OPERATION => 8,

      C_HAS_ABSOLUTE => 0,

      C_HAS_ACLKEN => 0,

      C_HAS_ADD => 0,

      C_HAS_ARESETN => 0,

      C_HAS_A_TLAST => 0,

      C_HAS_A_TUSER => 0,

      C_HAS_B => 1,

      C_HAS_B_TLAST => 0,

      C_HAS_B_TUSER => 0,

      C_HAS_COMPARE => 0,

      C_HAS_DIVIDE => 0,

      C_HAS_DIVIDE_BY_ZERO => 0,

      C_HAS_EXPONENTIAL => 0,

      C_HAS_FIX_TO_FLT => 0,

      C_HAS_FLT_TO_FIX => 0,

      C_HAS_FLT_TO_FLT => 0,

      C_HAS_INVALID_OP => 0,

      C_HAS_LOGARITHM => 0,

      C_HAS_MULTIPLY => 1,

      C_HAS_OPERATION => 0,

      C_HAS_OPERATION_TLAST => 0,

      C_HAS_OPERATION_TUSER => 0,

      C_HAS_OVERFLOW => 0,

      C_HAS_RECIP => 0,

      C_HAS_RECIP_SQRT => 0,

      C_HAS_RESULT_TLAST => 0,

      C_HAS_RESULT_TUSER => 0,

      C_HAS_SQRT => 0,

      C_HAS_SUBTRACT => 0,

      C_HAS_UNDERFLOW => 0,

      C_LATENCY => 1,

      C_MULT_USAGE => 2,

      C_OPERATION_TDATA_WIDTH => 8,

      C_OPERATION_TUSER_WIDTH => 1,

      C_OPTIMIZATION => 1,

      C_RATE => 1,

      C_RESULT_FRACTION_WIDTH => 24,

      C_RESULT_TDATA_WIDTH => 32,

      C_RESULT_TUSER_WIDTH => 1,

      C_RESULT_WIDTH => 32,

      C_THROTTLE_SCHEME => 3,

      C_TLAST_RESOLUTION => 0,

      C_XDEVICEFAMILY => "kintex7"

    );

-- synthesis translate_on

BEGIN

-- synthesis translate_off

U0 : wrapped_mulFP1

  PORT MAP (

    aclk => aclk,

    s_axis_a_tvalid => s_axis_a_tvalid,

    s_axis_a_tdata => s_axis_a_tdata,

    s_axis_b_tvalid => s_axis_b_tvalid,

    s_axis_b_tdata => s_axis_b_tdata,

    m_axis_result_tvalid => m_axis_result_tvalid,

    m_axis_result_tdata => m_axis_result_tdata

  );

-- synthesis translate_on

END mulFP1_a;