Modeltest.vhd

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-- Company: 

-- Engineer:

--

-- Create Date:   09:25:42 12/26/2009

-- Design Name:   

-- Module Name:   D:/VHDL TUTORIAL/SIMULATOR_PULS/Modeltest.vhd

-- Project Name:  SIMULATOR_PULS

-- Target Device:  

-- Tool versions:  

-- Description:   

-- 

-- VHDL Test Bench Created by ISE for module: FLASH_CONTROLLER

-- 

-- Dependencies:

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes: 

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test.  Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation 

-- simulation model.

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY Modeltest IS

END Modeltest;

ARCHITECTURE behavior OF Modeltest IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT FLASH_CONTROLLER

    PORT(

         FLASH_RESET : IN  std_logic;

         FLASH_CLK : IN  std_logic;

         FLASH_ADD : OUT  std_logic_vector(23 downto 0);

         FLASH_RP : OUT  std_logic;

         FLASH_CE : OUT  std_logic;

         FLASH_OE : OUT  std_logic;

         FLASH_DATA : IN  std_logic_vector(7 downto 0);

         DATAOUT : OUT  std_logic_vector(11 downto 0)

        );

    END COMPONENT;

   --Inputs

   signal FLASH_RESET : std_logic := '0';

   signal FLASH_CLK : std_logic := '0';

   signal FLASH_DATA : std_logic_vector(7 downto 0) := (others => '0');

   --Outputs

   signal FLASH_ADD : std_logic_vector(23 downto 0);

   signal FLASH_RP : std_logic;

   signal FLASH_CE : std_logic;

   signal FLASH_OE : std_logic;

   signal DATAOUT : std_logic_vector(11 downto 0);

   -- Clock period definitions

   constant FLASH_CLK_period : time := 100 ns;

BEGIN

  -- Instantiate the Unit Under Test (UUT)

   uut: FLASH_CONTROLLER PORT MAP (

          FLASH_RESET => FLASH_RESET,

          FLASH_CLK => FLASH_CLK,

          FLASH_ADD => FLASH_ADD,

          FLASH_RP => FLASH_RP,

          FLASH_CE => FLASH_CE,

          FLASH_OE => FLASH_OE,

          FLASH_DATA => FLASH_DATA,

          DATAOUT => DATAOUT

        );

   -- Clock process definitions

   FLASH_CLK_process :process

   begin

    FLASH_CLK <= '0';

    wait for FLASH_CLK_period/2;

    FLASH_CLK <= '1';

    wait for FLASH_CLK_period/2;

   end process;

   -- Stimulus process

   stim_proc: process

   begin

     FLASH_RESET <= '1';

     wait for 125 ns;

     FLASH_RESET <= '0';

      wait;

   end process;

END;