main.c

//*----------------------------------------------------------------------------

// main.c

// Testprogramm für das TFT-Display KWH040GM05-F02

// 480 x 272 Pixel

// 

// Hardware: LPC2478 @ 72MHz, SDRAM IS42S32400B (ISSI, 4M x 32)

//

// v1.0, Januar 2010, Erwin Reuss

//*----------------------------------------------------------------------------

#include "tools.h"

//*----------------------------------------------------------------------------

#define SDRAM_BASE_ADDR    0xA0000000

#define SDRAM_SIZE    0x01000000

//*----------------------------------------------------------------------------

void EMC_Init(void)

{

  u32 i;

  EMC_CTRL = 0x00000001;    /*Disable Address mirror*/

  PCONP   |= 0x00000800;    /* Turn On EMC PCLK */

  PINSEL5   = 0x55010115;

  PINSEL6   = 0x55555555;

  PINSEL7   = 0x55555555;

  PINSEL8   = 0x15555555;

  PINSEL9   = (1 << 18);

  EMC_DYN_RP     = 2;    /* command period: 3(n+1) clock cycles */

  EMC_DYN_RAS    = 3;    /* RAS command period: 4(n+1) clock cycles */

  EMC_DYN_SREX   = 7;    /* Self-refresh period: 8(n+1) clock cycles */

  EMC_DYN_APR    = 2;    /* Data out to active: 3(n+1) clock cycles */

  EMC_DYN_DAL    = 5;    /* Data in to active: 6(n+1) clock cycles */

  EMC_DYN_WR     = 1;    /* Write recovery: 2(n+1) clock cycles */

  EMC_DYN_RC     = 5;    /* Active to Active cmd: 6(n+1) clock cycles */

  EMC_DYN_RFC    = 5;    /* Auto-refresh: 6(n+1) clock cycles */

  EMC_DYN_XSR    = 7;    /* Exit self-refresh: 8(n+1) clock cycles */

  EMC_DYN_RRD    = 1;    /* Active bank A->B: 2(n+1) clock cycles */

  EMC_DYN_MRD    = 2;    /* Load Mode to Active cmd: 3(n+1) clock cycles */

  EMC_DYN_RD_CFG = 1;    /* Command delayed strategy */

  /* Default setting, RAS latency 3 CCLKs, CAS latenty 3 CCLKs. */

  EMC_DYN_RASCAS0 = 0x00000303;

  EMC_DYN_CFG0    = (1 << 14) | (0 << 12) | (2 << 9) | (2 << 7); // 4M x 32 in 4 banks

  delayMs(0, 100);

  /* Mem clock enable, CLKOUT runs, send command: NOP */

  EMC_DYN_CTRL = 0x00000183;

  delayMs(0, 200);

  /* Send command: PRECHARGE-ALL, shortest possible refresh period */

  EMC_DYN_CTRL = 0x00000103;

  /* set 32 CCLKs between SDRAM refresh cycles */

  EMC_DYN_RFSH = 0x00000002;

  for(i = 0; i < 0x40; i++);  /* wait 128 AHB clock cycles */

  /* set 28 x 16CCLKs=448CCLK=7us between SDRAM refresh cycles */

  EMC_DYN_RFSH = 28;

  /* Mem clock enable, CLKOUT runs, send command: MODE */

  EMC_DYN_CTRL = 0x00000083;

  /* Set mode register in SDRAM */

  i = *((volatile DWORD *)(SDRAM_BASE_ADDR | (0x032 << 12)));

  EMC_DYN_CTRL  = 0x00000000;    /* Send command: NORMAL */

  EMC_DYN_CFG0 |= 0x00080000;    /* Enable buffer */

}

//*----------------------------------------------------------------------------

// LCD INIT

//*----------------------------------------------------------------------------

#define LCD_CFG      (*(volatile unsigned long *)0xE01FC1B8)

#define LCD_TIMH    (*(volatile unsigned long *)0xFFE10000)

#define LCD_TIMV    (*(volatile unsigned long *)0xFFE10004)

#define LCD_POL      (*(volatile unsigned long *)0xFFE10008)

#define LCD_UPBASE      (*(volatile unsigned long *)0xFFE10010)

#define LCD_LPBASE        (*(volatile unsigned long *)0xFFE10014)

#define LCD_CTRL    (*(volatile unsigned long *)0xFFE10018)

#define CRSR_CTRL    (*(volatile unsigned long *)0xFFE10C00)

//*----------------------------------------------------------------------------

#define x_size    480

#define y_size    272

#define FRAMEBUF  0xA0000000

//*----------------------------------------------------------------------------

void Lcd_Init(void)

{

  PINSEL0  |= 0x00055500;

  PINSEL3  |= 0x05555500;

  PINSEL4  |= 0x050FFFFF;

  PINSEL9  |= 0x0A000000;

  PINSEL11 |= 0x0000000B;

  PCONP |= BIT(20);

  LCD_CTRL = BIT(5) | (6 << 1);  // TFT-5:6:5 Bit

  LCD_CFG  = 7;             // CCLK/8 = 9 Mhz

  LCD_POL  = (0x01 << 26)   // Bypass clock divider

           | ((x_size - 1) << 16) // Clock per Line

           | (0x00 << 14)   // ENA aktiv low

           | (0x00 << 13)   // DATA falling edge

           | (0x01 << 12)   // HSYNC aktiv low

           | (0x01 << 11);  // VSYNC aktiv low

  LCD_TIMH = (1  << 24)     // Horizontal back porch (2)

           | (1  << 16)     // Horizontal front porch (2)

           | (40 << 8)      // Horizontal pulse width (41)

           | (((x_size / 16) - 1) << 2);  // Pixels per Line

  LCD_TIMV = (2  << 24)     // Vertical back porch (3)

           | (2  << 16)     // Vertical front porch (3)

           | (9  << 10)     // Vertical pulse width (10)

           | (y_size - 1);  // Vertical lines

  LCD_UPBASE = FRAMEBUF;

  LCD_LPBASE = 0;

  LCD_CTRL |= BIT(11) | 0x01;

}

//*----------------------------------------------------------------------------

//  24-Bit Farbtabelle für Farbbalken

//*----------------------------------------------------------------------------

const u32 coltab[] = { 0x00FFFFFF, 0x0000FFFF, 0x00FFFF00, 0x0000FF00,

                       0x00FF00FF, 0x000000FF, 0x00FF0000, 0x00000000 };

//*----------------------------------------------------------------------------

// Programm beginnt hier

//*----------------------------------------------------------------------------

int main(void)

{

  u32 *ptr = (u32 *)0xA0000000;

  u32 x, y;

  EMC_Init();

  Lcd_Init();

  while((u32)ptr < 0xA1000000) {  // Kompletten Speicher löschen

    *ptr++ = 0x00000000;

  }

  // Farbbalken anzeigen  

  ptr = (u32 *)0xA0000000;

  for(y = 0; y < y_size; y++) {

    for(x = 0; x < x_size; x++) {

      ptr[y * 480 + x] = coltab[x / 60];

    }

  }

  while(true) {                   // Endlosschleife...

  }

}

//*----------------------------------------------------------------------------