bench.vhd

-------------------------------------------------------------------------------

-- Company: 

-- Engineer:

--

-- Create Date:   11:33:42 02/26/2010

-- Design Name:   

-- Module Name:   C:/Xilinx/Simulator/Simulator_Version01/Bench.vhd

-- Project Name:  Simulator_Version01

-- Target Device:  

-- Tool versions:  

-- Description:   

-- 

-- VHDL Test Bench Created by ISE for module: Flanken_Detektierung_AD_Wandler

-- 

-- Dependencies:

-- 

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes: 

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test.  Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation 

-- simulation model.

--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

ENTITY Bench IS

END Bench;

ARCHITECTURE behavior OF Bench IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Flanken_Detektierung_AD_Wandler

    PORT(

         Eingang_Flanken_Detektierung_AD_Wandler      : IN  std_logic_vector(11 downto 0);

         Clk_20Mhz_Flanken_Detektierung               : IN  std_logic;

         Analoge_Maximale_Amplitude_AD_Wandler        : OUT std_logic_vector(11 downto 0);

         Analoge_Flanke_wurde_erkannt_vom_AD_Wandler  : OUT std_logic

        );

    END COMPONENT;

   --Inputs

   signal Eingang_Flanken_Detektierung_AD_Wandler     : std_logic_vector(11 downto 0) := (others => '0');

   signal Clk_20Mhz_Flanken_Detektierung              : std_logic := '0';

   --Outputs

   signal Analoge_Maximale_Amplitude_AD_Wandler       : std_logic_vector(11 downto 0);

   signal Analoge_Flanke_wurde_erkannt_vom_AD_Wandler : std_logic;

   -- Clock period definitions

   constant Clk_20Mhz_Flanken_Detektierung_period     : time := 50000 ps;

BEGIN

  -- Instantiate the Unit Under Test (UUT)

   uut: Flanken_Detektierung_AD_Wandler PORT MAP (

          Eingang_Flanken_Detektierung_AD_Wandler     => Eingang_Flanken_Detektierung_AD_Wandler,

          Clk_20Mhz_Flanken_Detektierung              => Clk_20Mhz_Flanken_Detektierung,

          Analoge_Maximale_Amplitude_AD_Wandler       => Analoge_Maximale_Amplitude_AD_Wandler,

          Analoge_Flanke_wurde_erkannt_vom_AD_Wandler => Analoge_Flanke_wurde_erkannt_vom_AD_Wandler

        );

   -- Clock process definitions

   Clk_20Mhz_Flanken_Detektierung <= not Clk_20Mhz_Flanken_Detektierung after Clk_20Mhz_Flanken_Detektierung_period/2;

   -- Stimulus process

   stim_proc: process

   begin    

      -- hold reset state for 10 clock cycles

      wait for Clk_20Mhz_Flanken_Detektierung_period*10;  

      -- insert stimulus here 

      for count in 1 to 10 loop

        -- generate triangle wave

        for i in 0 to 2**12-1 loop

          Eingang_Flanken_Detektierung_AD_Wandler <= std_logic_vector(to_unsigned(i, Eingang_Flanken_Detektierung_AD_Wandler'length));

          wait until rising_edge(Clk_20Mhz_Flanken_Detektierung);

        end loop;

        for i in 2**12-1 downto 0 loop

          Eingang_Flanken_Detektierung_AD_Wandler <= std_logic_vector(to_unsigned(i, Eingang_Flanken_Detektierung_AD_Wandler'length));

          wait until rising_edge(Clk_20Mhz_Flanken_Detektierung);

        end loop;

      end loop;

      wait;

   end process;

END;