1 | #include "lpc2468_registers.h"
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2 | #define CR 0x0D
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3 | #define IER_RBR 0x01
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4 | #define IER_THRE 0x02
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5 | #define IER_RLS 0x04
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6 |
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7 | int SendChar(char c)
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8 | {
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9 | if (c == '\n')
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10 | {
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11 | while (!(U0LSR & 0x20));
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12 | U0THR = CR;
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13 | }
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14 | while (!(U0LSR & 0x20));
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15 | return (U0THR = c);
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16 | }
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17 |
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18 | void SendString(char *str)
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19 | {
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20 | SendChar(*str); // The first byte
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21 | while (*str++) // All further bytes
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22 | {
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23 | SendChar(*str);
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24 | }
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25 | }
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26 |
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27 | char ReadChar()
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28 | {
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29 | while ((U0LSR & 1) == 0); // Auf "Receiver Data Ready"-Bit (RDR) im "Line Status Register" (LSR) warten
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30 | return U0RBR; // Byte vom Stack einlesen ("Receiver Buffer Register", RBR)
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31 | }
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32 |
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33 | void InitUART0()
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34 | {
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35 | PCONP |= (1 << 3); // UART0 power on
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36 | PINSEL0 |= 0x00000050; // P0.2 TXD0, P0.3 RXD0
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37 | U0FDR = 0; // Fractional divider not used
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38 | U0LCR = 0x83; // 8 bits, no Parity, 1 Stop bit and enable access to divisor latches
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39 | U0DLL = 97; // 9600 Baud Rate @ 15 MHz VPB Clock
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40 | U0DLM = 0; // High divisor latch = 0
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41 | U0LCR = 0x03; // DLAB = 0 and enable access to U0IER
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42 | PCLKSEL0 &= 0xFFFFFF7F; // clock selection for UART0
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43 | U0FCR = 0x07; // for UART0: RX and TX FIFO reset and FIFO enable
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44 | }
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45 |
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46 | void UART0ISR (void)
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47 | {
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48 | SendString("Character received!\n");
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49 | VICVectAddr = 0; // Acknowledge Interrupt
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50 | }
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51 |
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52 | void InitUART0Interrupt()
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53 | {
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54 | U0IER = 0x00; // disable all interrupts
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55 | VICIntEnClr = 0xFFFFFFFF; // delete all interrupts
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56 | VICIntSelect |= 0x00000000; // select uart0 interrupt source as IRQ (not FIQ)
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57 | VICVectAddr0 = (unsigned long)UART0ISR; // address of the ISR
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58 | VICVectCntl0 |= ((1<<5) | 6); // VIC enable and channel 6 (weißt evntl. VICVectAdr0 den uart0-interrupt zu???)
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59 | VICIntEnable |= (1<<6); // select uart0 in interrupt enable clear register
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60 |
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61 | U0IER = (IER_RBR | IER_THRE | IER_RLS | 0x03); // Enable UART0 interrupt
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62 | }
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