clock.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity clock is

port( clk: in std_logic;

  reset:in std_logic;

   sel : in std_logic;

        a: out std_logic);

end clock;

architecture Behavioral of clock is

signal cnt:std_logic_vector(1 downto 0);

begin

counter: process (reset,clk)

begin

  if reset='1' then

    cnt<=(others=>'0');

  elsif rising_edge(clk) then

    cnt<=cnt+1;

  end if;

end process;

mux: process (sel,clk,cnt)

begin

  a<=cnt(0);

  if (sel='1') then

    a<=clk;

  end if;

end process;

end Behavioral;