Error loading design (Modelsim student version)

[Keltuzad (Guest)]

Hi @ all,

Im working with the student version of Modelsim, I have dowloaded the 
latest version (6.5b) and the licence and copied it to the root 
folder(C:\dev\Modeltech_pe_edu_6.5b).

Now to the problem:

Im using "vsim -voptargs=+acc work.tdm_bert_tb" as my run command.
My only error report is:
#Error loading design

Due to the limited content of the error msg I have difficulties finding 
a solution.

What have I already done:
I have reinstalled Modelsim + licence with Administrator rights, tried 
running it with different -commands e.g. vsim -optargs work.tdm_bert_tb, 
vsim work.tdm_bert_tb (none).
I only recieve the above mentoinened error.

Any suggestions are welcome.

Thanks in advance.

Kel.

[guest (Guest)]

did you compile your designfiles/tb into the work lib using vlib and 
vcom?

[Kel (Guest)]

hi,
yes all files including the testbench are compiled.

[Christian R. (supachris)]

In the most cases the error is shown many lines obove the "Error loading 
design" Message. Search the blue lines for "Fatal : ..." or so.

[Kel (Guest)]

Hi supachris,
thx for the hint but the only error line I recieve is the "#Error 
loading design" line and no other output. This is the fact that keeps me 
from investigating further.

[Anand Singh (Guest)]

I am getting the error "Error Load Design"(Modelsim student version).
I have three modules and all are compiling without errors.
However,the order for one of them (test bench) stays '0' in the left 
window.
Now,while trying to run the three modules,I was getting the error which 
I have specified above.

[Ottmar (Guest)]

If the topmodule isn't loadable, try the submodules one by one.

[Sentinel (Guest)]

Make sure that your PDF student license is contained in the 
C:\Modeltech_pe_edu_10.0c' directory folder only( i.e. is not contained 
in any subfolders, the 'win32pe_edu' folder in particular!). I tried 
this before and it cured the #Error loading system# for me when it 
appeared!

I hope this will cure some headaches aswell!

Regards,
Sentinel.

[Victoria (Guest)]

Hi,

I just had the same error message myself
and this is how I fixed it

#Error loading design

- Check your license is not in a sub folder especially 'win32pe_edu' in 
the  ModelSim directory

- and then check your "tb" design to see if your "module" and "uut" name 
are one and the same for example mine was

         module tb_ex1_gate();

and
         ex1 uut

This led to the error "#Error loading design" because ModelSim could not 
find it in the libraries, it should have been

         module tb_ex1_gate();

and
         ex1_gate uut

also when the this error appears you can find more detail when you 
scroll up on the Transcript section


I hope all this helps I am using ModelSim PE Student Edition 10.0c

[BVP (Guest)]

Thanks, Christian. Your input has helped me! Cheers..

[Anuj K. (anuj_k)]

Guys I solved my problem!
But first lets describe the problem
I was building a half subtractor using structural modelling. One of the 
components used a not gate and I named the component "NOTGATE", which 
was okay since it compiled peacefully.

But when i simulated the entity, an error occurred that said "Error 
loading Design".
I ran a google search and stumbled here. The guy named Christian on this 
post pointed out to check the lines above the error "FATAL...". Thanks 
christian!

I checked mine out and it said that the "entity" NOTGATE was causing 
problem which was in the same folder as the entity of half subtractor. I 
checked the folder and I remembered "Oh yeah! I had once made that 
entity (practicing you know!)." So i went back to my program and renamed 
the component NOTGATE as NOTG. Simulated it and it executed without a 
problem!

<Conclusion:
1. Read the whole error message not just the error line!
2. Always try to use unique identifiers in you program :/

[karim (Guest)]

hi I have same Error which is error loading design
there is no any problem in my code also the licen. file was downloaded 
in my computer but i dont know the problem that make my modelsim doesnot 
run the code is there any one has the solve thanks

[Lothar M. (Company: Titel) (lkmiller) (Moderator)]

> there is no any problem in my code
You seem to be very confident about that. What gives you that certitude?

>> The guy named Christian on this post pointed out to check the lines
>> above the error "FATAL..."
What error messages do you get previous to the fatal error?

[akaryas (Guest)]

This do not solve my problem...

# Compile of TB_Add1b.vhd was successful.
# Compile of Add1b.vhd was successful.
# Compile of config_Add1b.vhd was successful.
# 3 compiles, 0 failed with no errors.

ModelSim > vsim -voptargs=+acc -t ns work.cfg_test
# vsim -voptargs=+acc -t ns work.cfg_test
# Error loading design

[Cheroot (Guest)]

Kel wrote:
> hi,
> yes all files including the testbench are compiled.

[Cheroot (Guest)]

Loding...

[maryam (Guest)]

module Alsu8bit (a,b,cin,s3,s2,s1,s0,z);
     input [7:0]a,b;
     input cin,s3,s2,s1,s0;
output [7:0]z;
wire cout;
 wire [7:0] au,lu,shr,shl;
au8bit   au0 (a[7:0],b[7:0],cin,s1,s0,cout,au[7:0]);
lu8bit   lu0(a[7:0],b[7:0],s1,s0,lu[7:0]);
shru8bit shr0 (a[7:0],1'b1,s1,s0,shr[7:0]);
shlu8bit shl0 (a[7:0],1'b1,s1,s0,shl[7:0]);
mux8bit  alsu (au[7:0],lu[7:0],shr[7:0],shl[7:0],s3,s2,z[7:0]);
endmodule

[mukul (Guest)]

hi,
i got the same error and i saved the license file in 
C:\Modeltech_pe_edu_10.4a . it would be very helpful if anybody let me 
know wht should i do to remove this error

[Sharan (Guest)]

Hello. This is my code of full subtractor using 2 half subtractors. No 
error in compiling. but there is this error will simulating the program:


Port w and d are not found in the connection module.



module hs(diff,borrow,a,b);
  output diff,borrow;
  input a,b;
  assign diff= a^b;
  assign borrow= ~a&b;
endmodule
module fs(diff,borrow,a,b,cin);
  output diff,borrow;
  input a,b,cin;
  wire [1:0]w,d;
  hs a1(.w(w[0]),.a(a),.d(d[0]),.b(b));
  hs a2(.a(d[0]),.d(d[1]),.b(cin),.w(w[1]));
  assign diff=d[1];
  assign borrow= w[0] | w[1];
endmodule


I will be obliged if you could help.

[Joseph (Guest)]

Here's another thought....

I had this problem after moving a simulation folder containing all my 
verilog and project files.  After opening the project file (*.mpf) in a 
text editor, I found all verilog files were described with absolut path 
names, NOT relative path names. A simple find & replace to correct the 
path would fix it!

[Alex Cole (Guest)]

Joseph wrote:
> Here's another thought....
>
> I had this problem after moving a simulation folder containing all my
> verilog and project files.  After opening the project file (*.mpf) in a
> text editor, I found all verilog files were described with absolut path
> names, NOT relative path names. A simple find & replace to correct the
> path would fix it!

This is the correct fix for most of these errors. It's another one of 
ModelSim's wonderful "quirks", of which there seem to be an infinite 
amount!

[Saad (Guest)]

* Error: (vsim-3053) C:/Users/Uzma/Desktop/fedup/fsm_tb.v(9): Illegal 
output or inout port connection for "port 'out'".
#

Plz help as i dont understand the meaning of this error.. output port 
has been clearly identified but still its not loading the file...

[Saad (Guest)]

// My FSM TB Code
module fsm_tb;

reg clk,rst;

reg din;

reg out;

fsm MUT(din,rst,clk,.out(out));

initial

clk<=1;

always

#5 clk <=  ~(clk);

//Set occurance of sequence
initial
begin
@(posedge clk);     din <= 1'b1 ;
@(posedge clk);     din <= 1'b0 ;
@(posedge clk);     din <= 1'b0 ;
@(posedge clk);     din <= 1'b1 ;
@(posedge clk);     din <= 1'b1 ;
@(posedge clk);     din <= 1'b0 ;
@(posedge clk);     din <= 1'b1 ;
@(posedge clk);     din <= 1'b0 ;
@(posedge clk);     din <= 1'b1 ;

end

endmodule

[Duke Scarring (Guest)]

$ vlog fsm_tb.v
Model Technology ModelSim SE-64 vlog 10.3d Compiler 2014.10 Oct  7 2014
Start time: 12:00:36 on Nov 21,2016
vlog fsm_tb.v
-- Compiling module fsm_tb
** Error: fsm_tb.v(10): near ".": syntax error, unexpected '.', expecting ')'
End time: 12:00:36 on Nov 21,2016, Elapsed time: 0:00:00
Errors: 1, Warnings: 0

After changing ".out(out)" to "my_out(out)", I got the following output:

$ vlog fsm_tb.v
Model Technology ModelSim SE-64 vlog 10.3d Compiler 2014.10 Oct  7 2014
Start time: 12:01:41 on Nov 21,2016
vlog fsm_tb.v
-- Compiling module fsm_tb

Top level modules:
        fsm_tb
End time: 12:01:41 on Nov 21,2016, Elapsed time: 0:00:00
Errors: 0, Warnings: 0

Duke

[Avani (Guest)]

It worked for me

[Eduardo Hernandez (Guest)]

************************************************************************ 
*
Author: Sentinel (Guest)
Posted on: 2011-10-06 17:15
Make sure that your PDF student license is contained in the
C:\Modeltech_pe_edu_10.0c' directory folder only( i.e. is not contained
in any subfolders, the 'win32pe_edu' folder in particular!). I tried
this before and it cured the #Error loading system# for me when it
appeared!

I hope this will cure some headaches aswell!

Regards,
Sentinel.
************************************************************************ 
*
Sentinel

YOU ARE A GENIUS !
COOL!

[y.parhizkar (Guest)]

thanks, it was very helpful!

[Unanimous (Guest)]

Maybe somebody already mentioned it but just to be sure, after you've 
saved the license file in the right directory as described in previous 
posts, close ModelSim and then try again to simulate because otherwise 
the error won't disappear

[SUMIT (Guest)]

please help don't know what to do

[SUMIT (Guest)]

Error loading design (Modelsim student version)

[rafi (Guest)]

Thanks ,it works

[rafi (Guest)]

this method works..

[Rajesh (Guest)]

i am keep on getting error loading design error after when i click on 
simulate
i have tried some things
but i was not able to correct
could someone explain it briefly how can i solve this problem

[Seimen (Guest)]

My code has been compiled successfully but on simulating the following 
error is shown. Please help in rectifying the error.

vsim -gui work.half_adder
# vsim
# Start time: 21:24:16 on Oct 13,2018
# Error loading design

[Duke Scarring (Guest)]

Here are the basic steps for using modelsim from command line:

1. Create library (working directory for modelsim):
$ vlib work

2. Compile design:
$ vcom design.vhd
Start time: 11:18:20 on Oct 16,2018
vcom design.vhd
Model Technology ModelSim SE-64 vcom 10.6c Compiler 2017.07 Jul 26 2017
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity design
-- Compiling architecture rtl of design
End time: 11:18:20 on Oct 16,2018, Elapsed time: 0:00:00
Errors: 0, Warnings: 0

3. Compile testbench:
$ vcom testbench.vhd
Start time: 11:19:23 on Oct 16,2018
vcom testbench.vhd
Model Technology ModelSim SE-64 vcom 10.6c Compiler 2017.07 Jul 26 2017
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity testbench
-- Compiling architecture testbench of testbench
End time: 11:19:23 on Oct 16,2018, Elapsed time: 0:00:00
Errors: 0, Warnings: 0

4. Start simulator:
$ vsim -gui testbench

5. Add some signals to view:
VSIM 1> add wave *

6. Run simulator for a specified time:
VSIM 2> run 1 ms

7. Zoom the wave window:
VSIM 3> wave zoom full
# {0 ps} {1050 us}

Duke

[Fezzeni Nejla (Guest)]

plz any aide

[Fezzeni Nejla (Guest)]

any aide

[Fezzeni Nejla (Guest)]

help with the error massage: error loading design

[hyannistoolman (Guest)]

Thanks guys, matching these names and then redefining in the simulation 
file settings solved this problem for me.

[Ram (Guest)]

Checks: 1.student license must be in the same folder of ModelSim
        2.If not cut and paste it.
        3.run the simulation
If you have done above things but still getting same.Then
        Uninstall ModelSim and again reinstall it.

[cyberwalker (Guest)]

You were SOOOO right about the license path! Thank you so much!

[Arslan (Guest)]

My work library will not work proper.when i will compile it will add 
another work library in compile and show the work library empty.Anyone 
can tell me the problem.

[Shubham Agra (Guest)]

I had the same problem for almost 2 months now. This is how i solved it:

For those trying gate level simulation and using a sdf file along with 
it, you must also compile the sdf file. But it not like compiling any 
other file. You must use the command sdfcom. Also when using this 
command, you must also specify the sdo file name as input, and a new 
file name that will be used as output file. So the syntax goes like:

sdfcom [ options ] source-file output-file

This might help some people.
I am using Modelsim FPGA Starter version 10.5b

Thanx

[Supriya (Guest)]

hi,
i am even getting same erroe and in the blue line it's written
( Error: (vsim-3173) Entity 
'C:/Modeltech_pe_edu_10.4a/CourseraFPGA/Course2/AAC2M1P1/work.comparator 
2'  has no architecture)
Please suggest what should i do.

[Supriya B. (Company: Lovely Professional University) (supriya_18)]

Hi,
I am getting error due to loading design and the reason given is 
"comparator 2 has no architecture".Please help me out.I had attached the 
file also'

[Andi (Guest)]

# vsim
# Start time: 11:53:42 on Oct 20,2020
# Error loading design

this is the error that keeps showing when i try to simulate my codes
module bufif_notif_gates (output c,d, input a, b);
bufif1 (c, a, b);
notif1 (d, a, b);
endmodule
module bufif_notif_gates_tb;
  reg tb_a, tb_b;
  wire tb_c, tb_d;
  bufif_notif_gates_tb Instance0 (tb_c, tb_d, tb_a, tb_b);
  initial begin
    tb_a = 0; tb_b = 0;
 #1 tb_a = 0; tb_b = 1;
 #1 tb_a = 1; tb_b = 0;
 #1 tb_a = 1; tb_b = 1;
  end
  initial begin
    $monitor ("T=%t| a=%b |b=%b| c(bufif)=%b |d(notif)=%b", $time, tb_a, 
tb_b, tb_c, tb_d);
  end
endmodule

this is my code. i don't know how to fix this :(

[Duke Scarring (Guest)]

You need three steps to simulate in modelsim:

1. create library:
vlib work

2. compile all design files (and the testbench!) into the library (work 
is the default):
vlog my_design.v
vlog my_testbench.v

3. start simulation:
vsim -gui my_testbench

That's it.
Duke

[anusha (Guest)]

how to fix this prblm?


 //
# vsim -gui
# Start time: 00:25:07 on Dec 06,2020
# Loading work.tb_1101moore_74
# ** Error: (vsim-3033) C:/Modeltech_pe_edu_10.4a/examples/TB_310.v(13): 
Instantiation of 'moore1101' failed. The design unit was not found.
#    Time: 0 ns  Iteration: 0  Instance: /tb_1101moore_74 File: 
C:/Modeltech_pe_edu_10.4a/examples/TB_310.v
#         Searched libraries:
#             C:/Modeltech_pe_edu_10.4a/examples/work
# Error loading design
vlog -reportprogress 300 -work work 
C:/Modeltech_pe_edu_10.4a/examples/TB_310.v
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 
2015.03 Apr  7 2015
# Start time: 00:27:50 on Dec 06,2020
# vlog -reportprogress 300 -work work 
C:/Modeltech_pe_edu_10.4a/examples/TB_310.v
# -- Compiling module tb_1101moore_74
#
# Top level modules:
#   tb_1101moore_74
# End time: 00:27:50 on Dec 06,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

[Lothar M. (Company: Titel) (lkmiller) (Moderator)]

anusha wrote:
> # ** Error: (vsim-3033) C:/Modeltech_pe_edu_10.4a/examples/TB_310.v(13):
> Instantiation of 'moore1101' failed. The design unit was not found.
How does line 13 of TB_310.v look like?

[anusha (Guest)]

this is my test bench

[Lothar M. (Company: Titel) (lkmiller) (Moderator)]

anusha wrote:
> this is my test bench
I'm sorry, I won't open a doc file.
Pls. simply attach VHDL files as *.VHDL files.

[anusha (Guest)]

when i complile it was like this

vlog -work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L 
infact -O0 C:/Modeltech_pe_edu_10.4a/examples/TB_310.v
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 
2015.03 Apr  7 2015
# Start time: 14:53:12 on Dec 07,2020
# vlog -reportprogress 300 -work work -L mtiAvm -L mtiRnm -L mtiOvm -L 
mtiUvm -L mtiUPF -L infact -O0 
C:/Modeltech_pe_edu_10.4a/examples/TB_310.v
# -- Compiling module tb_moore1101_74
#
# Top level modules:
#   tb_moore1101_74
# End time: 14:53:12 on Dec 07,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

[Duke Scarring (Guest)]

Did you have compile moore1101.v also?

Duke

[Paulpraveen P. (paulpraveen23)]

Damm even I am having a similar kind of issue, I have searched all over 
the internet and even have posted on number of threads on different 
forum, no solution seems to work. I am really frustrated, can anyone of 
you here help me resolve this issue, I am very much tired now.

[Duke Scarring (Guest)]

Paulpraveen P. wrote:
> Damm even I am having a similar kind of issue,
New Problem -> new question.
And without specific and detailed error description only people with a 
working crystal ball can help.

Duke

[Lerninstructor (Guest)]

Paulpraveen P. wrote:
> I am really frustrated, can anyone of
> you here help me resolve this issue, I am very much tired now.

As pointed out in this old posting: 
https://embdev.net/topic/error-loading-design-modelsim-student-version#6511390
the cause of the error is "Not all required source files are compiled" .

[Lerninstructor (Guest)]

Also check, if all working libraries are created and active (see command 
'vlib' and 'vmap').

[Rahul P. (Company: Webcorewin) (rahulp411)]

I have three modules and all are compiling without errors.
However,the order for one of them (test bench) stays '0' in the left
window.
Now,while trying to run the three modules,I was getting the error which
I have specified above.

[Lerninstructor (Guest)]

Rahul P. wrote:
> I have three modules and all are compiling without errors.

> Now,while trying to run the three modules,I was getting the error which
> I have specified above.

Again, check library references ('use'-clause, instance-component 
references) as described above.

[Paulpraveen P. (paulpraveen23)]

Duke Scarring wrote:
> Paulpraveen P. wrote:
>> Damm even I am having a similar kind of issue,
> New Problem -> new question.
> And without specific and detailed error description only people with a
> working crystal ball can help.
>
> Duke

Should I start a new thread or post it here anyway? cz I'm unable to 
find a suitable thread for it.

[Lothar M. (Company: Titel) (lkmiller) (Moderator)]

Paulpraveen P. wrote:
> Should I start a new thread
Do so.
And write more than "I have problems".