AT91SAM7S64 "PLL" als "Main Clock" Problem

[romanua (Gast)]

[C]
@;Select Master, PLL, PIO, USB
clock--------------------------------------------

        @; enable main
oscillator-----------------------------------------------
        ldr r0, =CKGR_MOR                @;main oscillator register
address
        ldr r7, =1<<CKGR_MOR_MOSCEN_BIT|7<<CKGR_MOR_OSCOUNT_BIT
                                         @;MOSC enable and Start-up
time
        str r7, [r0]

@;----------------------------------------------------------------------



        @; wait for MOSC to start
up--------------------------------------------
wait1:  ldr r0, =PMC_SR
        ldr r1,[r0]
        tst r1, #PMC_SR_MOSCS
        beq wait1

@;----------------------------------------------------------------------


        @; configure PLL with MUL=73(72+1), DIV=14,
USBDIV=2--------------------
        @; PLL_COUNT=7,
PLLR_OUT=0----------------------------------------------
        ldr r0, =CKGR_PLLR
        ldr r1,
=72<<CKGR_PLLR_MUL_BIT|14<<CKGR_PLLR_DIV_BIT|2<<CKGR_PLLR_USBDIV_BIT|16< 
<CKGR_PLLR_PLLCOUNT_BIT|0<<CKGR_PLLR_OUT_BIT
        str r1, [r0]

@;----------------------------------------------------------------------


        @; wait for PLL to
lock-------------------------------------------------
wait2:  ldr r0, =PMC_SR
        ldr r1,[r0]
        tst r1, #PMC_SR_LOCK
        beq wait2

@;----------------------------------------------------------------------



        @; select Master Clock source and
prescaler-----------------------------
        ldr r0, =PMC_MCKR
        ldr r1, =1<<PMC_MCKR_PRES_BIT
        str r1, [r0]                       @; prescaler set

        @;wait for masterclock to stabilize
wait3:  ldr r3, =PMC_SR
        ldr r4,[r3]
        tst r4, #PMC_SR_MCKRDY
        beq wait3                          @;not resolved issue: after
                                           @;prescaler set MCKRDY does

                                           @;not come up;

        ldr r2, =0b11<<PMC_MCKR_CSS_BIT
        orr r2, r2, r1
        str r2, [r0]                       @; MCK Source set

        @;wait for master clock ready bit to set
wait4:  ldr r0, =PMC_SR
        ldr r1,[r0]
        tst r1, #PMC_SR_MCKRDY
        beq wait4

@;----------------------------------------------------------------------
[\C]

Hallo, ich programiere einen AT91SAM7S64 und moechte PLL als main clock
 einstellen. Das Programm bleibt bei "wait3___beq wait3" stehen (oder
besser gesagt- kreist), d.h. MCKRDY bit nicht hochkommt. Woran kann es
liegen?

[romanua (Gast)]

Hallo,

mein Main Oscillator ist 18,432Mhz.

[romanua (Gast)]

Ich habe die Loesung gefunden. Man soll nach den Einstellen von PLL
einmal auf LOCK bit warten und einmal  PMC_SR_MCKRDY.


wait2:  ldr r0, =PMC_SR
        ldr r1,[r0]
        tst r1, #PMC_SR_LOCK
        beq wait2
@;----------------------------------------------------
wait21: ldr r3, =PMC_SR
        ldr r4,[r3]
        tst r4, #PMC_SR_MCKRDY
        beq wait21
@;----------------------------------------------------

        ldr r0, =PMC_MCKR
        ldr r1, =1<<PMC_MCKR_PRES_BIT
        str r1, [r0]

        @;wait for masterclock to stabilize
wait3:  ldr r3, =PMC_SR
        ldr r4,[r3]
        tst r4, #PMC_SR_MCKRDY
        beq wait3

Warum der Schritt notwendig ist weiss ich nicht, ich habe es bei
BasicUSB von Atmel abgeguckt. Im Datenblatt steht nur, dass man auf
PMC_SR_LOCK warten muss.