-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cpu is port(

      clk  : in  std_logic;
      ena  : in  std_logic;
      nrs  : in  std_logic;
      rep  : in  std_logic;

      n3 : out std_logic;
      n2 : out std_logic;
      n1 : out std_logic;
      n0 : out std_logic;

      datbus : inout std_logic_vector ( 7 downto 0);
      adrbus : inout std_logic_vector (15 downto 0) );

end cpu;
architecture behcpu of cpu is

  signal  pha, p1a, p2a, p3a, p5a,
          qhb, q1b, q2b, q3b, q4b, qkb   : std_logic := '0';
  signal  iha, i1a, i2a, i3a, i5a,
          ihb, i1b, i2b, i3b, i4b, ikb   : std_logic;

  signal  act, bbb, pzz, opz1, fff1, nfh1, nf23       : std_logic := '0';

  signal  ee1, ee2, ee3, opa, opb       : std_logic_vector ( 7 downto 0);
  signal  eep, ppp, rrr, qqq, nnn       : std_logic_vector (15 downto 0);

  signal  vvv, tww, ffa        : std_logic;

  signal  kka, kkb, dda, hha, taa, tbb   : std_logic_vector ( 7 downto 0);
  signal  sss, xxx, yyy, zzz, tcd        : std_logic_vector (15 downto 0);

  signal  ccvs, ccus, ccas, ccks, ccss,
          cc1s, cc2s, cc3s, cccs, cou , abw   : std_logic;

  signal  muopb, mue2, muaa, mubb, muka, mukb : std_logic_vector ( 7 downto 0);
  signal  munn, mupp, murr, mucd, muss, muxz  : std_logic_vector (15 downto 0);
  signal  sum, dab, dcd, muadr                : std_logic_vector (15 downto 0);

  signal  aat, datout                         : std_logic_vector ( 7 downto 0);
  signal  kkt, adrout                         : std_logic_vector (15 downto 0);

  signal  en3, en2, en1, en0              : std_logic;
  signal  kn3, kn2, kn1, kn0              : std_logic := '0';
  signal  adrena, datena                  : std_logic := '0';

  signal  outa, outk, outp, outr, outx, outy, outz, outd,
          wnn, ennpp, ennrr, ennkk,
          we2, wopb, wccc, nccc, eccvs, eccus, eccas, eccks, eccss,
          wtab, nta, ntb, etabs, etaa, etab, etava, etaav, etae1, etat,
          etba, etbb, etbvb, etbbv, etbe1, etbop, wcd, ncd, ecdt,
          ecds, ecdk, ecdx, ecdy, ecdz, ecdp, ecdr, ecdq,
          wtw, ntw, etwv, etwa0, etwa7, etwb0, etwb7,

          t1et1, t1et2, t1et3, t1et4, t1et5, t1et6, t1et7,
          t1eaa, t1ebb, t2ebb, t1eab, t1eba, t1eava, t1eaav, t1ebvb, t1ebbv,
          t1eat, t1ebop, t2eae1, t2ebe1, t1eabs, t1na, t2na, t1nb, t2nb,
          t1ecdk, t2ecdk, t1ecdx, t2ecdx, t1ecdy, t2ecdy, t1ecdz, t2ecdz,
          t1ecdt, t1ecds, t1ecdp, t2ecdp, t1ecdq, t2ecdr, t1ncd, t2ncd,
          t1ewv, t1ewu,  t1nw,   t2nw,
          t1ncc, t1eccv, t1eccu, t1ecca, t1ecck, t1eccs,
          t1oup, t1oupo, t1our, t1ouro, t1ouk, t1oux, t1ouy, t1ouz, t1oua,
          t1sn2, t2sn2, t3sn2, t1sn1, t1sn0, thsn0,

          p1eaa, p1ebb, p2ebb, p1eab, p1eba, p1eava, p1eaav, p1ebvb, p1ebbv,
          p1eat, p1ebop, p2eae1, p2ebe1, p1eabs, p1na, p2na, p1nb, p2nb,
          p1ecdk, p2ecdk, p1ecdx, p2ecdx, p1ecdy, p2ecdy, p1ecdz, p2ecdz,
          p1ecdt, p1ecds, p1ecdp, p2ecdp, p1ecdq, p2ecdr, p1ncd, p2ncd,
          p1ewv, p1ewu,  p1nw,   p2nw,
          p1ncc, p1eccv, p1eccu, p1ecca, p1ecck, p1eccs,
          p1oup,         p1our,         p1ouk, p1oux, p1ouy, p1ouz, p1oua,
          p1sn2, p2sn2, p3sn2, p1sn1, p1sn0, phsn0              : std_logic;

  signal  wpp, epsum, wrr, wqq,
          we1, we3, wopa, wfa, wha,
          wvv, evvw, evvzo, evvcy, evvcn,
          wka, ekaa, ekac, ekad, ekasu, ekant, ekaxr, ekaw,
          wkb, ekbb, ekbc, ekbd, ekbsu,
          wss, essdab, essiab, essab, esscd,
          wxx, wyy, wzz, exztab, exzdcd, exzicd, exzsum,

          f1kaa, f2kaa, f1kac, f1kad, f1kasu, f2kasu, f1kant, f2kant,
          f1kaxr, f2kaxr, f1kaw, f1kbb, f1kbc, f1kbd, f1kbsu, f2kbsu,
          f1vw, f1vnz, f1vcy, f2vcy, f1vcn, f2vcn,
          f1wx, f2wx, f1wy, f2wy, f1wz, f2wz,
          f1xzab, f1xzdc, f1xzic, f1xzsu, f2xzsu,
          f1ssda, f3ssda, f1ssia, f1ssab, f1sscd,
          f1pin, f1psu, f2psu, f1rn, f2rn, f1qcd,
          f1opa,
          f1sef, f2sef, f3sef, f1opz,
          f1sn2, f1sn1, f1sn0,

          q1kaa, q2kaa, q1kac, q1kad, q1kasu, q2kasu, q1kant, q2kant,
          q1kaxr, q2kaxr, q1kaw, q1kbb, q1kbc, q1kbd, q1kbsu, q2kbsu,
          q1vw, q1vnz, q1vcy, q2vcy, q1vcn, q2vcn,
          q1wx, q2wx, q1wy, q2wy, q1wz, q2wz,
          q1xzab, q1xzdc, q1xzic, q1xzsu, q2xzsu,
          q1ssda, q3ssda, q1ssia, q1ssab, q1sscd,
          q1pin, q1psu, q2psu, q1rn, q2rn, q1qcd,
          q1opa,
          q1sef, q2sef, q3sef, q1opz,
          q1sn2, q1sn1, q1sn0         : std_logic;

-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
--phasen-ringzaehler

  i5a <= p5a when rep = '1' else q4b;
  iha <= pha when rep = '1' else opz1 and not t1ouk;
  i1a <= p1a when rep = '1' else fff1 or (opz1 and t1ouk);
  i2a <= p2a when rep = '1' else nfh1;
  i3a <= p3a when rep = '1' else nf23;

  i4b <= q4b when rep = '1' else pzz;
  ikb <= '0' when rep = '1' else pha;
  ihb <= qhb when rep = '1' else bbb;
  i1b <= q1b when rep = '1' else p1a or p5a;
  i2b <= q2b when rep = '1' else p2a;
  i3b <= q3b when rep = '1' else p3a;

pact : process (clk) begin if clk'event and clk = '1' then if ena = '1' then
       act <= not rep;
       end if; end if; end process pact;

pdnn : process (clk) begin if clk'event and clk = '1' then if ena = '1' then
       pha <= iha and nrs; p1a <= i1a and nrs;
       p2a <= i2a and nrs; p3a <= i3a and nrs;
       qhb <= ihb and nrs; q1b <= i1b and nrs;
       q2b <= i2b and nrs; q3b <= i3b and nrs;
       q4b <= i4b and nrs; p5a <= i5a and nrs;
       qkb <= ikb and nrs; pzz <= not nrs;
       end if; end if; end process pdnn;

--end phasen-ringzaehler;
-------------------------------------------------------------------------------
--regfhb

wfhb : process (clk) begin if clk'event and clk = '0' then if ena = '1' then

  bbb  <=  pha and phsn0;
  opz1 <=  q1b and q1opz;
  fff1 <= (q1b and q1sef) or (q2b and q2sef) or (q3b and q3sef) or qhb;
  nfh1 <=  q1b and not (q1sef or q1opz);
  nf23 <= (q2b and not q2sef) or (q3b and not q3sef);

       end if; end if; end process wfhb;

--end regfhb;
-------------------------------------------------------------------------------
--perip

  n3 <= kn3; n2 <= kn2; n1 <= kn1; n0 <= kn0;

  adrbus <= adrout  when adrena = '1' else "ZZZZZZZZZZZZZZZZ";
  datbus <= datout  when datena = '1' else "ZZZZZZZZ";

acti : process (clk) begin if clk'event and clk = '0' then if ena = '1' then
       kn3 <= en3; kn2 <= en2; kn1 <= en1; kn0 <= en0;
       adrena <= act and outa;
       datena <= act and outd;
       end if; end if; end process acti;

writeadrout : process (clk) begin if clk'event and clk = '0' then
              if (outa and ena) = '1' then
              adrout <= muadr; end if; end if; end process writeadrout;

writedatout : process (clk) begin if clk'event and clk = '0' then
              if (outd and ena) = '1' then
              datout <= kka;   end if; end if; end process writedatout;

adressmu : process (kka, kkb, ppp, rrr, xxx, yyy, zzz,
                    outk, outp, outr, outx, outy, outz)

  variable kkk, voutk, voutp, voutr,
                voutx, vouty, voutz : std_logic_vector (15 downto 0);
  variable o  : std_logic;    begin   kkk := kka & kkb;

  o := outk; voutk :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := outp; voutp :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := outr; voutr :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := outx; voutx :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := outy; vouty :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := outz; voutz :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;

  muadr <= (voutk and kkk) or (voutp and ppp) or (voutr and rrr) or
           (voutx and xxx) or (vouty and yyy) or (voutz and zzz);

  end process adressmu;

writeep : process (clk) begin
          if clk'event and clk = '1' then if (pzz and ena) = '1' then
          eep <= adrbus; end if; end if;
          end process writeep;

--end perip;
-------------------------------------------------------------------------------
--e1e2e3

writee1 : process (clk) begin
          if clk'event and clk = '0' then if (we1 and ena) = '1' then
          ee1 <= datbus; end if; end if;
          end process writee1;

writee2 : process (clk) begin
          if clk'event and clk = '0' then if (we2 and ena) = '1' then
          ee2 <= mue2;   end if; end if;
          end process writee2;

writee3 : process (clk) begin
          if clk'event and clk = '0' then if (we3 and ena) = '1' then
          ee3 <= std_logic_vector(unsigned(ee2)-1); end if; end if;
          end process writee3;

  mue2 <= ee1 when p2a = '1' else ee3;

  we1  <= act and q1b;
  we2  <= p2a or  p3a;
  we3  <= q2b or  q3b;

--end e1e2e3;
-------------------------------------------------------------------------------
--opabc

          ccvs <= vvv;

          ccus <= kka(7);
          ccas <= kka(7) or kka(6) or kka(5) or kka(4) or
                  kka(3) or kka(2) or kka(1) or kka(0) ;
          ccks <= kka(7) or kka(6) or kka(5) or kka(4) or
                  kka(3) or kka(2) or kka(1) or kka(0) or
                  kkb(7) or kkb(6) or kkb(5) or kkb(4) or
                  kkb(3) or kkb(2) or kkb(1) or kkb(0) ;

          ccss <= sss(15) or sss(14) or sss(13) or sss(12) or
                  sss(11) or sss(10) or sss( 9) or sss( 8) or
                  sss( 7) or sss( 6) or sss( 5) or sss( 4) or
                  sss( 3) or sss( 2) or sss( 1) or sss( 0) ;

          cc1s <= ee1(7) or ee1(6) or ee1(5) or ee1(4) or
                  ee1(3) or ee1(2) or ee1(1) or ee1(0) ;
          cc2s <= ee2(7) or ee2(6) or ee2(5) or ee2(4) or
                  ee2(3) or ee2(2) or ee2(1) or ee2(0) ;
          cc3s <= ee3(7) or ee3(6) or ee3(5) or ee3(4) or
                  ee3(3) or ee3(2) or ee3(1) or ee3(0) ;

writeccc : process (clk)     begin
  if clk'event and clk = '0' then if (wccc and ena) = '1' then
  cccs <= ((eccvs and ccvs) or (eccus and ccus) or (eccas and ccas) or
           (eccks and ccks) or (eccss and ccss )) xor nccc;
  end if; end if; end process writeccc;

writeopa : process (clk)     begin
  if clk'event and clk = '0' then if (wopa and ena) = '1' then opa <= datbus;
  end if; end if; end process writeopa;

writeopb : process (clk)     begin
  if clk'event and clk = '0' then if (wopb and ena) = '1' then opb <= muopb;
  end if; end if; end process writeopb;

  muopb <= opa when p5a = '0' else x"c8";

--end opabc;
-------------------------------------------------------------------------------
--prnq

writeqq : process (clk)      begin
  if clk'event and clk = '0' then if (wqq and ena) = '1' then qqq <= tcd;
  end if; end if; end process writeqq;

writepp : process (clk)      begin
  if clk'event and clk = '0' then if (wpp and ena) = '1' then ppp <= mupp;
  end if; end if; end process writepp;

  mupp <= sum when epsum = '1' else std_logic_vector(unsigned(nnn)+1);

writerr : process (clk)      begin
  if clk'event and clk = '0' then if (wrr and ena) = '1' then rrr <= murr;
  end if; end if; end process writerr;

  murr <= eep when q4b   = '1' else nnn;

writenn : process (clk)      begin
  if clk'event and clk = '0' then if (wnn and ena) = '1' then nnn <= munn;
  end if; end if; end process writenn;

pmunn : process (ennpp, ennrr, ennkk, ppp, rrr, kka, kkb)

  variable kkk, vennpp, vennrr, vennkk : std_logic_vector (15 downto 0);
  variable      o                      : std_logic;

  begin         kkk := kka & kkb;

  o := ennpp; vennpp :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ennrr; vennrr :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ennkk; vennkk :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;

  munn <= (vennpp and ppp) or (vennrr and rrr) or (vennkk and kkk);
  end process pmunn;

--end prnq;
-------------------------------------------------------------------------------
--regab

writeta : process (clk)      begin
  if clk'event and clk = '0' then if (wtab and ena) = '1' then taa <= muaa;
  end if; end if; end process writeta;

writetb : process (clk)      begin
  if clk'event and clk = '0' then if (wtab and ena) = '1' then tbb <= mubb;
  end if; end if; end process writetb;

maat : process (t1et1, t1et2, t1et3, t1et4, t1et5, t1et6, t1et7, kka)

  variable vet1, vet2, vet3, vet4, vet5, vet6, vet7,
           t1, t2, t3, t4, t5, t6, t7    : std_logic_vector (7 downto 0);

  variable o  : std_logic;           begin

  t1 := kka(6 downto 0) & kka(7         );
  t2 := kka(5 downto 0) & kka(7 downto 6);
  t3 := kka(4 downto 0) & kka(7 downto 5);
  t4 := kka(3 downto 0) & kka(7 downto 4);
  t5 := kka(2 downto 0) & kka(7 downto 3);
  t6 := kka(1 downto 0) & kka(7 downto 2);
  t7 := kka(0         ) & kka(7 downto 1);

  o := t1et1; vet1 :=  o & o & o & o & o & o & o & o;
  o := t1et2; vet2 :=  o & o & o & o & o & o & o & o;
  o := t1et3; vet3 :=  o & o & o & o & o & o & o & o;
  o := t1et4; vet4 :=  o & o & o & o & o & o & o & o;
  o := t1et5; vet5 :=  o & o & o & o & o & o & o & o;
  o := t1et6; vet6 :=  o & o & o & o & o & o & o & o;
  o := t1et7; vet7 :=  o & o & o & o & o & o & o & o;

  aat <= (vet1 and t1) or (vet2 and t2) or (vet3 and t3) or
         (vet4 and t4) or (vet5 and t5) or (vet6 and t6) or (vet7 and t7);

  end process maat;

pmuaa : process (etaa, etab, etae1, etabs, etava, etaav,
                 etat, nta, vvv, kka, kkb, ee1, sss, aat)

  variable vetaa, vetab, vetae1, vetabs, vetava, vetaav,
           vetat, vnta, va, av, hs        : std_logic_vector (7 downto 0);

  variable o  : std_logic;           begin

  va := vvv & kka(7 downto 1); av := kka(6 downto 0) & vvv;

  hs := sss(15 downto 8);

  o := nta  ; vnta   :=  o & o & o & o & o & o & o & o;
  o := etaa ; vetaa  :=  o & o & o & o & o & o & o & o;
  o := etab ; vetab  :=  o & o & o & o & o & o & o & o;
  o := etae1; vetae1 :=  o & o & o & o & o & o & o & o;
  o := etabs; vetabs :=  o & o & o & o & o & o & o & o;
  o := etava; vetava :=  o & o & o & o & o & o & o & o;
  o := etaav; vetaav :=  o & o & o & o & o & o & o & o;
  o := etat ; vetat  :=  o & o & o & o & o & o & o & o;

  muaa <= vnta xor ((vetaa  and kka) or (vetab  and kkb) or
                    (vetae1 and ee1) or (vetabs and hs ) or
                    (vetava and va ) or (vetaav and av ) or (vetat and aat));

  end process pmuaa;

pmubb : process (etba, etbb, etbvb, etbbv, etbop, etabs, etbe1,
                             ntb, vvv, kka, kkb, ee1, opa, sss)

  variable vb, bv, ls, o3, vetba, vetbb, vetbvb, vetbbv, vetbop,
           vetabs, vetbe1, vntb : std_logic_vector (7 downto 0);

  variable o  : std_logic;        begin

  o3(7) := '0' ; o3(6) := '0'   ; o3(5) := '0'   ; o3(4) := '0'   ;
  o3(3) := '0' ; o3(2) := opa(2); o3(1) := opa(1); o3(0) := opa(0);

  vb := vvv & kkb(7 downto 1); bv := kkb(6 downto 0) & vvv;

  ls := sss(7 downto 0);

  o := ntb  ; vntb   :=  o & o & o & o & o & o & o & o;
  o := etba ; vetba  :=  o & o & o & o & o & o & o & o;
  o := etbb ; vetbb  :=  o & o & o & o & o & o & o & o;
  o := etbvb; vetbvb :=  o & o & o & o & o & o & o & o;
  o := etbbv; vetbbv :=  o & o & o & o & o & o & o & o;
  o := etbop; vetbop :=  o & o & o & o & o & o & o & o;
  o := etabs; vetabs :=  o & o & o & o & o & o & o & o;
  o := etbe1; vetbe1 :=  o & o & o & o & o & o & o & o;

  mubb <= vntb xor ((vetba and kka) or (vetbb and kkb) or
                    (vetbvb and vb) or (vetbbv and bv) or
                    (vetbop and o3) or (vetabs and ls) or (vetbe1 and ee1));

  end process pmubb;

--end regab;
-------------------------------------------------------------------------------
--regcd

writetcd : process (clk)     begin
  if clk'event and clk = '0' then if (wcd and ena) = '1' then tcd <= mucd;
  end if; end if; end process writetcd;

mkkt : process (t1et1, t1et2, t1et3, t1et4, t1et5, t1et6, t1et7, kka, kkb)

  variable vet1, vet2, vet3, vet4, vet5, vet6, vet7,
           kkk, t1, t2, t3, t4, t5, t6, t7   : std_logic_vector (15 downto 0);

  variable o  : std_logic;

  begin                     kkk := kka & kkb;

  t1 := kkk(14 downto 0) & kkk(15          );
  t2 := kkk(13 downto 0) & kkk(15 downto 14);
  t3 := kkk(12 downto 0) & kkk(15 downto 13);
  t4 := kkk(11 downto 0) & kkk(15 downto 12);
  t5 := kkk(10 downto 0) & kkk(15 downto 11);
  t6 := kkk( 9 downto 0) & kkk(15 downto 10);
  t7 := kkk( 8 downto 0) & kkk(15 downto  9);

  o := t1et1; vet1 :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := t1et2; vet2 :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := t1et3; vet3 :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := t1et4; vet4 :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := t1et5; vet5 :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := t1et6; vet6 :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;
  o := t1et7; vet7 :=   o & o & o & o & o & o & o & o
                      & o & o & o & o & o & o & o & o;

  kkt <=  (vet1 and t1) or (vet2 and t2) or (vet3 and t3) or
          (vet4 and t4) or (vet5 and t5) or (vet6 and t6) or (vet7 and t7);

  end process mkkt;

pmucd : process (ecdk, ecds, ecdq, ecdp, ecdr, ecdx, ecdy, ecdz, ecdt,
                 ncd, kka, kkb, sss, xxx, yyy, zzz, ppp, rrr, qqq, kkt)

  variable vecdk, vecds, vecdq, vecdp, vecdr, vecdx, vecdy, vecdz,
           vecdt, vncd,  kkk           : std_logic_vector (15 downto 0);

  variable o : std_logic;

  begin                     kkk := kka & kkb;

  o := ncd  ; vncd   :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ecdk ; vecdk  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ecds ; vecds  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ecdq ; vecdq  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ecdp ; vecdp  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ecdr ; vecdr  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ecdx ; vecdx  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ecdy ; vecdy  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ecdz ; vecdz  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := ecdt ; vecdt  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;

  mucd <= vncd xor ((vecdk and kkk) or (vecds and sss) or (vecdq and qqq) or
                    (vecdp and ppp) or (vecdr and rrr) or (vecdt and kkt) or
                    (vecdx and xxx) or (vecdy and yyy) or (vecdz and zzz));

  end process pmucd;

--end regcd;
-------------------------------------------------------------------------------
--regww

writetww : process (clk)     begin
  if clk'event and clk = '0' then if (wtw and ena) = '1' then

  tww <= ntw xor ((etwv and vvv) or
         (etwa0 and kka(0)) or (etwa7 and kka(7)) or
         (etwb0 and kkb(0)) or (etwb7 and kkb(7)));

  end if; end if; end process writetww;

--end regww;
-------------------------------------------------------------------------------
--arith

komb : process (tww, taa, tbb, tcd)

  variable tab           : std_logic_vector (15 downto 0);
  variable eab, ecd, esm : std_logic_vector (17 downto 0);

  variable uab, ucd, usm : unsigned(17 downto 0);

begin   tab := taa & tbb;

        eab := '0' & tab & tww ;
        ecd := '0' & tcd & '1' ;
        uab := unsigned(eab);
        ucd := unsigned(ecd);
        usm := uab + ucd;
        esm := std_logic_vector(usm);

        cou <= esm(17);
        sum <= esm(16 downto 1);

        dab <= std_logic_vector(unsigned(tab)-1);
        dcd <= std_logic_vector(unsigned(tcd)-1);

  end process komb;

--end arith;
-------------------------------------------------------------------------------
--regvv

writevv : process (clk)      begin
  if clk'event and clk = '0' then if (wvv and ena) = '1' then

  vvv <= (evvw  and tww) or (evvcy and cou) or (evvcn and not cou) or
         (evvzo and abw);

  end if; end if; end process writevv;

  abw <= taa(7) or taa(6) or taa(5) or taa(4) or
         taa(3) or taa(2) or taa(1) or taa(0) or
         tbb(7) or tbb(6) or tbb(5) or tbb(4) or
         tbb(3) or tbb(2) or tbb(1) or tbb(0) or tww;

--end regvv;
-------------------------------------------------------------------------------
--regkk

wha <= act and (qhb or q4b); wfa <= wka or wha;

kka <= dda  when  ffa = '1'  else  hha;

writeka : process (clk)      begin
  if clk'event and clk = '0' then if (wka and ena) = '1' then dda <= muka;
  end if; end if; end process writeka;

writeha : process (clk)      begin
  if clk'event and clk = '0' then if (wha and ena) = '1' then hha <= datbus;
  end if; end if; end process writeha;

writefa : process (clk)      begin
  if clk'event and clk = '0' then if (wfa and ena) = '1' then ffa <= wka;
  end if; end if; end process writefa;

writekb : process (clk)      begin
  if clk'event and clk = '0' then if (wkb and ena) = '1' then kkb <= mukb;
  end if; end if; end process writekb;

pmuka : process (ekaw, ekaa, ekac, ekad, ekasu, ekant, ekaxr,
                                         tww, taa, tcd, sum)

  variable  twa, tcc, tdd, suh, vekaw, vekaa, vekac, vekad,
            vekasu, vekant, vekaxr :   std_logic_vector (7 downto 0);

  variable o  : std_logic;    begin

  twa := tww & taa(6 downto 0);
  tcc := tcd(15 downto 8);
  tdd := tcd( 7 downto 0);
  suh := sum(15 downto 8);

  o := ekaw ; vekaw  :=  o & o & o & o & o & o & o & o;
  o := ekaa ; vekaa  :=  o & o & o & o & o & o & o & o;
  o := ekac ; vekac  :=  o & o & o & o & o & o & o & o;
  o := ekad ; vekad  :=  o & o & o & o & o & o & o & o;
  o := ekasu; vekasu :=  o & o & o & o & o & o & o & o;
  o := ekant; vekant :=  o & o & o & o & o & o & o & o;
  o := ekaxr; vekaxr :=  o & o & o & o & o & o & o & o;

  muka <= (vekaa  and taa) or (vekac  and tcc) or (vekad and tdd) or
                              (vekasu and suh) or (vekaw and twa) or
          (vekant and taa and not tcc) or (vekaxr and (taa xor tcc));

  end process pmuka;

pmukb : process (ekbb, ekbc, ekbd, ekbsu, tbb, tcd, sum)

  variable  tcc, tdd, sul,
            vekbb, vekbc, vekbd, vekbsu : std_logic_vector (7 downto 0);

  variable o  : std_logic;    begin

  tcc := tcd(15 downto 8);
  tdd := tcd( 7 downto 0);
  sul := sum( 7 downto 0);

  o := ekbb ; vekbb  :=  o & o & o & o & o & o & o & o;
  o := ekbc ; vekbc  :=  o & o & o & o & o & o & o & o;
  o := ekbd ; vekbd  :=  o & o & o & o & o & o & o & o;
  o := ekbsu; vekbsu :=  o & o & o & o & o & o & o & o;

  mukb <= (vekbb  and tbb) or (vekbc  and tcc) or
          (vekbd  and tdd) or (vekbsu and sul);

  end process pmukb;

--end regkk;
-------------------------------------------------------------------------------
--regss

writess : process (clk)      begin
  if clk'event and clk = '0' then if (wss and ena) = '1' then sss <= muss;
  end if; end if; end process writess;

pmuss : process (essdab, essiab, essab, esscd, taa, tbb, tcd, dab)

  variable tab, veab, vecd, vedab, veiab  : std_logic_vector (15 downto 0);

  variable o  : std_logic;      begin            tab := taa & tbb;

  o := essab ; veab  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := esscd ; vecd  :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := essdab; vedab :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := essiab; veiab :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;

  muss <= (veab  and tab) or (vecd  and tcd) or
          (vedab and dab) or (veiab and not dab);
  end process pmuss;

--end regss;
-------------------------------------------------------------------------------
--regxz

writex : process (clk)       begin
  if clk'event and clk = '0' then if (wxx and ena) = '1' then xxx <= muxz;
  end if; end if; end process writex;

writey : process (clk)       begin
  if clk'event and clk = '0' then if (wyy and ena) = '1' then yyy <= muxz;
  end if; end if; end process writey;

writez : process (clk)       begin
  if clk'event and clk = '0' then if (wzz and ena) = '1' then zzz <= muxz;
  end if; end if; end process writez;

pmuxz : process (exztab, exzsum, exzdcd, exzicd, taa, tbb, sum, dcd)

  variable tab, vetab, vesum, vedcd, veicd  : std_logic_vector (15 downto 0);
  variable o                                : std_logic;

  begin            tab := taa & tbb;

  o := exztab; vetab :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := exzsum; vesum :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := exzdcd; vedcd :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;
  o := exzicd; veicd :=   o & o & o & o & o & o & o & o
                        & o & o & o & o & o & o & o & o;

  muxz <= (vetab and tab) or (vesum and sum) or
          (vedcd and dcd) or (veicd and not dcd);

  end process pmuxz;

--end regxz;
-------------------------------------------------------------------------------
--steua

elementea : process (opa, ccvs, ccus, ccas, ccks, ccss, cccs, cc1s, cc3s)

  variable  s7, s6, s5, s4, s3, s2, s1, s0 : std_logic;
  variable  z7, z6, z5, z4, z3, z2, z1, z0 : std_logic;
  variable  ccvz, ccuz, ccaz, cckz, ccsz   : std_logic;
  variable  xxxx, zzzz                     : std_logic;

begin

s7 := opa(7); s6 := opa(6); s5 := opa(5); s4 := opa(4);
s3 := opa(3); s2 := opa(2); s1 := opa(1); s0 := opa(0);

z7 := not s7; z6 := not s6; z5 := not s5; z4 := not s4;
z3 := not s3; z2 := not s2; z1 := not s1; z0 := not s0;

ccvz := not ccvs; ccuz := not ccus;
ccaz := not ccas; cckz := not ccks; ccsz := not ccss;

t1et1  <= (                                   z2 and z1 and s0) ;
t1et2  <= (                                   z2 and s1 and z0) ;
t1et3  <= (                                   z2 and s1 and s0) ;
t1et4  <= (                                   s2 and z1 and z0) ;
t1et5  <= (                                   s2 and z1 and s0) ;
t1et6  <= (                                   s2 and s1 and z0) ;
t1et7  <= (                                   s2 and s1 and s0) ;

xxxx   := (z7 and z6 and z5 and z4 and z3               and s0) or
          (s7 and z6 and s5 and z4 and z3                     ) or
          (s7 and z6 and s5               and s2              ) or
          (s7 and z6 and s5               and z2 and z1 and z0) or
          (s7 and s6 and s5 and s4 and s3 and z2 and z1       ) or
          (z7 and s6 and z5 and s4 and z3 and s2 and z1 and s0) ;
zzzz   := (z7 and z6 and s5        and s3                     ) or
          (z7 and z6 and s5 and s4                            ) or
          (s7 and z6 and s5               and s2 and z1 and s0) or
          (s7 and z6 and s5 and z4 and z3        and z1 and s0) or
          (s7 and s6 and z5 and s4 and s3 and z2 and z1 and z0) or
          (z7 and s6 and z5                      and s1       ) ;

t1eaa  <= xxxx                                                  or
          (s7 and s6 and s5 and z4 and z3 and s2              ) or
          (s7 and s6 and s5        and z3 and z2 and s1 and s0) or
          (s7 and s6 and s5 and s4        and s2 and z1       ) ;
t1ebb  <= xxxx                                                  or
          (s7 and z6 and z5 and z4 and z3 and z2              ) or
          (s7 and s6 and s5        and z3 and z2 and z1 and s0) ;
t2ebb  <= (z7 and s6 and s5               and z2        and s0) or
          (z7 and s6 and s5               and z2 and s1       ) ;
t1eab  <= (s7 and s6 and z5 and s4 and s3 and s2              ) or
          (s7 and s6 and z5 and s4 and s3        and s1       ) or
          (s7 and z6 and z5 and z4 and z3                     ) ;
t1eba  <= (s7 and s6 and z5 and s4 and s3 and s2              ) or
          (s7 and s6 and z5 and s4 and s3        and s1       ) or
          (z7 and z6 and s5 and z4 and z3               and s0) ;
t1ebvb <= (s7 and s6 and s5 and z4 and s3 and z2 and z1 and z0) ;
t1ebbv <= (s7 and s6 and s5 and z4 and s3 and z2 and z1 and s0) ;
t1eava <= (s7 and s6 and s5 and z4 and s3 and z2 and s1 and z0) ;
t1eaav <= (s7 and s6 and s5 and z4 and s3        and s1 and s0) ;
t1eat  <= (s7 and z6 and z5 and z4 and s3                     ) ;
t1ebop <= (z7 and z6               and s3                     ) or
          (z7 and z6        and s4                            ) ;
t2eae1 <= (z7 and s6 and s5                                   ) ;
t2ebe1 <= (z7 and s6 and z5                                   ) ;
t1eabs <= (z7 and z6 and z5 and z4 and z3               and z0) or
          (s7 and z6 and s5        and s3 and z2 and z1 and s0) or
          (s7 and z6 and s5 and s4        and z2 and z1 and s0) or
          (s7 and s6 and z5 and z4 and s3                     ) or
          (s7 and s6 and z5        and s3 and z2 and z1       ) ;
t1na   <= zzzz                                                  or
          (s7 and z6 and z5 and z4 and z3        and s1 and s0) or
          (s7 and s6 and s5 and s4 and z3 and z2 and s1 and s0) or
          (s7 and s6 and s5 and z4 and z3 and z2 and s1 and z0 and ccvs) ;
t2na   <= (z7 and s6 and z5 and z4               and s1       ) or
          (z7 and s6 and z5        and z3 and z2 and s1       ) or
          (z7 and s6 and z5 and s4 and s3               and s0) or
          (z7 and s6 and s5                      and s1 and s0) ;
t1nb   <= zzzz                                                  or
          (s7 and z6 and z5 and z4 and z3 and z2 and s1       ) or
          (s7 and s6 and s5 and s4 and z3 and z2 and z1 and s0) or
          (s7 and s6 and s5 and s4        and s2 and z1 and z0) or
          (s7 and s6 and s5 and z4 and z3 and z2 and z1 and z0 and ccvs) ;
t2nb   <= (z7 and s6 and z5 and z4               and s1       ) or
          (z7 and s6 and z5        and z3 and z2 and s1       ) or
          (z7 and s6 and z5 and s4 and s3               and s0) or
          (z7 and s6 and s5               and z2 and s1       ) ;

t1ecdt <= (s7 and z6 and z5 and s4                            ) ;
t1ecds <= (s7 and z6 and s5 and z4 and z3                     ) or
          (s7 and s6 and z5 and s4 and z3 and z2 and z1       ) ;
t1ecdk <= (s7 and z6 and z5               and z2 and z1 and z0) or
          (s7 and z6 and z5 and z4 and z3                     ) or
          (s7 and s6 and s5 and s4 and s3 and z2 and s1 and s0) ;
t2ecdk <= (z7 and s6        and s4 and z3 and s2 and z1 and s0) or
          (z7 and s6        and s4 and s3 and z2 and z1       ) or
          (z7 and s6 and s5                                   ) ;
t1ecdx <= (z7 and z6        and z4 and s3                     ) or
          (       z6 and s5 and z4 and s3                     ) or
          (s7 and s6 and z5        and s3 and z2 and s1       ) or
          (s7 and s6 and z5 and s4        and z2 and s1       ) ;
t2ecdx <= (z7 and s6 and z5 and s4 and s3 and z2 and s1       ) ;
t1ecdy <= (z7 and z6        and s4 and z3                     ) or
          (       z6 and s5 and s4 and z3                     ) or
          (s7 and s6 and z5        and s3 and s2 and z1       ) or
          (s7 and s6 and z5 and s4        and s2 and z1       ) ;
t2ecdy <= (z7 and s6 and z5 and s4 and s3 and s2 and z1       ) ;
t1ecdz <= (z7 and z6        and s4 and s3                     ) or
          (       z6 and s5 and s4 and s3                     ) or
          (s7 and s6 and z5        and s3 and s2 and s1       ) or
          (s7 and s6 and z5 and s4        and s2 and s1       ) ;
t2ecdz <= (z7 and s6 and z5 and s4 and s3 and s2 and s1       ) ;
t1ecdp <= (z7 and s6 and z5                      and s1       ) or
          (z7 and s6 and z5 and s4 and z3 and s2 and z1 and s0) or
          (s7 and s6 and s5 and s4 and s3 and s2 and s1 and s0) ;
t2ecdp <= (z7 and s6 and z5 and z4                            ) or
          (z7 and s6 and z5 and s4 and z3 and z2              ) or
          (z7 and s6 and z5 and s4 and z3        and z1 and z0) ;
t1ecdq <= (s7 and s6 and s5 and s4 and s3 and s2 and s1 and z0) ;
t2ecdr <= (z7 and s6 and z5 and s4 and z3 and s2 and s1 and s0) ;
t1ncd  <= (s7 and z6 and z5 and z4 and z3        and z1 and s0) or
          (s7 and z6 and s5               and s2 and s1 and s0) or
          (s7 and z6 and s5 and z4 and z3        and s1 and s0) or
          (s7 and s6 and z5        and s3        and s1 and z0) or
          (s7 and s6 and z5        and s3 and s2        and z0) or
          (s7 and s6 and s5 and s4        and s2 and z1 and s0) or
          (s7 and s6 and s5 and s4 and s3 and z2        and s0) ;
t2ncd  <= (z7 and s6 and s5                      and z1 and s0) ;

t1ewv  <= (s7 and s6 and s5 and s4 and z3 and s2 and z1       ) or
          (s7 and z6        and z4 and z3 and z2              ) or
          (s7 and s6 and s5 and z4 and z3 and z2        and s0) or
          (s7 and s6 and s5 and z4 and s3 and s2 and z1 and s0) ;
t1ewu  <= (s7 and s6 and s5 and z4 and z3 and s2        and s0) or
          (s7 and s6 and s5 and z4 and s3        and s1 and s0) ;
t1nw   <= (z7 and z6 and z5        and s3                     ) or
          (z7 and z6 and z5 and s4                            ) or
          (z7 and s6 and z5 and s4 and z3 and s2 and z1 and s0) or
          (s7 and s6 and s5 and s4 and z3 and s2 and z1 and s0) or
          (s7 and z6 and s5               and s2        and s0) or
          (s7 and z6        and z4 and z3 and z2        and s0) or
          (s7 and s6 and s5 and z4        and s2 and z1       ) or
          (s7 and s6 and s5 and s4 and s3        and z1 and z0) or
          (s7 and s6 and s5 and z4        and s2 and s1 and s0 and ccvs) ;
t2nw   <= (z7 and s6 and z5 and z4               and z1       ) or
          (z7 and s6 and z5        and z3        and z1       ) or
          (z7 and s6 and z5 and s4 and s3               and z0) or
          (z7 and s6 and s5               and z2        and s0) ;

t1eccv <= (z7 and s6 and z5 and z4 and z3 and z2              ) ;
t1eccu <= (z7 and s6 and z5 and z4 and z3 and s2              ) ;
t1ecca <= (z7 and s6 and z5 and z4 and s3 and z2              ) ;
t1ecck <= (z7 and s6 and z5 and z4 and s3 and s2              ) ;
t1eccs <= (z7 and s6 and z5 and s4 and z3 and z2 and s1 and s0) or
          (s7 and s6 and z5 and z4 and s3 and s2              ) or
          (s7 and s6 and z5 and z4 and s3        and s1       ) or
          (s7 and s6 and z5 and z4 and s3               and s0) ;
t1ncc  <= (z7 and s6 and z5 and z4                      and z0) or
          (z7 and s6 and z5        and z3 and z2        and z0) or
          (z7 and s6 and z5 and s4 and z3 and z2 and z1       ) or
          (s7 and s6 and z5 and s4 and s3                     ) ;

t1oup  <= not (
          (z7 and s6 and s5        and s3                     ) or
          (z7 and s6 and s5 and s4                            ) or
          (s7 and s6 and z5 and z4                            ) or
          (s7 and s6 and s5 and s4 and s3 and s2 and s1 and s0));
t1our  <= (s7 and s6 and z5 and z4 and s3 and z2 and z1 and z0) ;
t1oupo <= (s7 and s6 and z5 and z4 and z3 and z2 and z1 and z0 and ccvs) or
          (s7 and s6 and z5 and z4 and z3 and z2 and z1 and s0 and ccvz) or
          (s7 and s6 and z5 and z4 and z3 and z2 and s1 and z0 and ccus) or
          (s7 and s6 and z5 and z4 and z3 and z2 and s1 and s0 and ccuz) or
          (s7 and s6 and z5 and z4 and z3 and s2 and z1 and z0 and ccas) or
          (s7 and s6 and z5 and z4 and z3 and s2 and z1 and s0 and ccaz) or
          (s7 and s6 and z5 and z4 and z3 and s2 and s1 and z0 and ccks) or
          (s7 and s6 and z5 and z4 and z3 and s2 and s1 and s0 and cckz) or
          (s7 and s6 and z5 and z4 and s3               and s0 and ccsz) or
          (s7 and s6 and z5 and z4 and s3        and s1        and ccsz) or
          (s7 and s6 and z5 and z4 and s3 and s2               and ccsz) ;
t1ouro <= (s7 and s6 and z5 and z4 and z3 and z2 and z1 and z0 and ccvz) or
          (s7 and s6 and z5 and z4 and z3 and z2 and z1 and s0 and ccvs) or
          (s7 and s6 and z5 and z4 and z3 and z2 and s1 and z0 and ccuz) or
          (s7 and s6 and z5 and z4 and z3 and z2 and s1 and s0 and ccus) or
          (s7 and s6 and z5 and z4 and z3 and s2 and z1 and z0 and ccaz) or
          (s7 and s6 and z5 and z4 and z3 and s2 and z1 and s0 and ccas) or
          (s7 and s6 and z5 and z4 and z3 and s2 and s1 and z0 and cckz) or
          (s7 and s6 and z5 and z4 and z3 and s2 and s1 and s0 and ccks) or
          (s7 and s6 and z5 and z4 and s3               and s0 and ccss) or
          (s7 and s6 and z5 and z4 and s3        and s1        and ccss) or
          (s7 and s6 and z5 and z4 and s3 and s2               and ccss) ;

t1ouk  <= (s7 and s6 and s5 and s4 and s3 and s2 and s1 and s0) ;
t1oux  <= (z7 and s6 and s5 and z4 and s3                     ) ;
t1ouy  <= (z7 and s6 and s5 and s4 and z3                     ) ;
t1ouz  <= (z7 and s6 and s5 and s4 and s3                     ) ;

t1oua  <= (z7 and s6 and s5        and s3 and z2 and z1 and z0) or
          (z7 and s6 and s5 and s4        and z2 and z1 and z0) ;

t1sn2  <= (z7 and s6 and z5                                   ) or
          (z7 and s6 and s5 and z4 and z3                     ) or
          (z7 and s6 and s5               and s2              ) or
          (z7 and s6 and s5                      and s1       ) or
          (z7 and s6 and s5                             and s0) or
          (s7 and s6 and s5 and s4 and z3 and s2 and s1 and z0) ;
t2sn2  <= (z7 and s6 and z5                                    and cccs) or
          (z7 and s6 and z5 and s4 and z3 and s2 and s1 and s0 and cc1s) ;
t3sn2  <= (z7 and s6 and z5 and s4 and z3 and s2 and s1 and s0 and cc3s) ;
t1sn1  <= (z7 and s6 and s5 and s4                            ) ;
t1sn0  <= (z7 and s6 and s5        and s3                     ) ;
thsn0  <= not
          (z7 and z6 and z5 and z4 and z3 and z2 and z1 and z0) ;

end process elementea;
----------------------
writep : process(clk) begin

  if clk'event and clk = '1' then if ena = '1' then

  p1eaa  <= t1eaa ;  p1ebb  <= t1ebb ;  p2ebb  <= t2ebb ;  p1eab  <= t1eab ;
  p1eba  <= t1eba ;  p1eava <= t1eava;  p1eaav <= t1eaav;  p1ebvb <= t1ebvb;
  p1ebbv <= t1ebbv;  p1eat  <= t1eat ;  p1ebop <= t1ebop;  p2eae1 <= t2eae1;
  p2ebe1 <= t2ebe1;  p1eabs <= t1eabs;  p1na   <= t1na  ;  p2na   <= t2na  ;
  p1nb   <= t1nb  ;  p2nb   <= t2nb  ;  p1ecdt <= t1ecdt;  p1ecds <= t1ecds;
  p1ecdk <= t1ecdk;  p2ecdk <= t2ecdk;  p1ecdx <= t1ecdx;  p2ecdx <= t2ecdx;
  p1ecdy <= t1ecdy;  p2ecdy <= t2ecdy;  p1ecdz <= t1ecdz;  p2ecdz <= t2ecdz;
  p1ecdp <= t1ecdp;  p2ecdp <= t2ecdp;                     p1ecdq <= t1ecdq;
  p2ecdr <= t2ecdr;  p1ncd  <= t1ncd ;  p2ncd  <= t2ncd ;  p1ewv  <= t1ewv ;
  p1nw   <= t1nw  ;  p2nw   <= t2nw  ;  p1eccv <= t1eccv;  p1eccu <= t1eccu;
  p1ecca <= t1ecca;  p1ecck <= t1ecck;  p1eccs <= t1eccs;  p1ncc  <= t1ncc ;
  p1oup  <= t1oup or t1oupo;            p1our  <= t1our or t1ouro;
  p1ouk  <= t1ouk ;  p1oux  <= t1oux ;  p1ouy  <= t1ouy ;  p1ouz  <= t1ouz ;
  p1oua  <= t1oua ;  p1sn2  <= t1sn2 ;  p2sn2  <= t2sn2 ;  p3sn2  <= t3sn2 ;
  p1sn1  <= t1sn1 ;  p1sn0  <= t1sn0 ;  phsn0  <= thsn0 ;  p1ewu  <= t1ewu ;

end if; end if; end process writep;
-----------------------------------

  outd  <=  p1a and p1oua;
  outk  <= (p1a and p1ouk)    or pha;
  outp  <= (p1a and p1oup)    or p2a or p3a;
  outr  <= (p1a and p1our)    or p5a;
  outx  <=  p1a and p1oux;
  outy  <=  p1a and p1ouy;
  outz  <=  p1a and p1ouz;
  outa  <=  p1a or p2a or p3a or p5a or pha;
  wnn   <=  p1a or p2a or p3a or p5a;
  ennpp <= (p1a and p1oup)    or p2a or p3a;
  ennrr <= (p1a and p1our)    or p5a;
  ennkk <=  p1a and p1ouk;

  wopb  <=  p1a  or p5a;
  wccc  <=  p1a  or p5a;
  nccc  <=  p1a and p1ncc ;
  eccvs <=  p1a and p1eccv;
  eccus <=  p1a and p1eccu;
  eccas <=  p1a and p1ecca;
  eccks <=  p1a and p1ecck;
  eccss <=  p1a and p1eccs;

  wtab  <=  p1a             or  p2a or  p3a;
  nta   <= (p1a and p1na)   or (p2a and p2na);
  ntb   <= (p1a and p1nb)   or (p2a and p2nb);
  etaa  <=  p1a and p1eaa ;
  etab  <=  p1a and p1eab ;
  etava <=  p1a and p1eava;
  etaav <=  p1a and p1eaav;
  etat  <=  p1a and p1eat ;
  etae1 <=  p2a and p2eae1;
  etba  <=  p1a and p1eba ;
  etbb  <= (p1a and p1ebb)  or (p2a and p2ebb);
  etbvb <=  p1a and p1ebvb;
  etbbv <=  p1a and p1ebbv;
  etbop <=  p1a and p1ebop;
  etbe1 <=  p2a and p2ebe1;
  etabs <= (p1a and p1eabs) or  p3a ;

  wcd   <=  p1a             or  p2a ;
  ncd   <= (p1a and p1ncd)  or (p2a and p2ncd) ;
  ecdt  <=  p1a and p1ecdt;
  ecds  <=  p1a and p1ecds;
  ecdk  <= (p1a and p1ecdk) or (p2a and p2ecdk);
  ecdx  <= (p1a and p1ecdx) or (p2a and p2ecdx);
  ecdy  <= (p1a and p1ecdy) or (p2a and p2ecdy);
  ecdz  <= (p1a and p1ecdz) or (p2a and p2ecdz);
  ecdp  <= (p1a and p1ecdp) or (p2a and p2ecdp);
  ecdr  <=  p2a and p2ecdr;
  ecdq  <=  p1a and p1ecdq;

  wtw   <=  p1a or  p2a;
  ntw   <= (p1a and p1nw )  or (p2a and p2nw );
  etwv  <= (p1a and p1ewv)  or (p2a and p2ebb);
  etwa0 <=  p1a and p1eava;
  etwa7 <=  p1a and p1ewu ;
  etwb0 <=  p1a and p1ebvb;
  etwb7 <=  p1a and p1ebbv;

--end steua;
-------------------------------------------------------------------------------
--steub

elementeb : process (opb, cccs, cc2s)

  variable  s7, s6, s5, s4, s3, s2, s1, s0 : std_logic;
  variable  z7, z6, z5, z4, z3, z2, z1, z0 : std_logic;
  variable  cc2z                           : std_logic;

  variable  h1kasu, h2kasu, h1kbsu, h2kbsu,
            f1xsu, f2xsu, f1xab, f1xdc, f1xic,
            f1ysu, f2ysu, f1yab, f1ydc, f1yic,
            f1zsu, f2zsu, f1zab, f1zdc, f1zic : std_logic;
begin

  s7 := opb(7); s6 := opb(6); s5 := opb(5); s4 := opb(4);
  s3 := opb(3); s2 := opb(2); s1 := opb(1); s0 := opb(0);

  z7 := not s7; z6 := not s6; z5 := not s5; z4 := not s4;
  z3 := not s3; z2 := not s2; z1 := not s1; z0 := not s0;

cc2z := not cc2s;

h1kbsu := (z7 and s6 and z5 and s4 and z3 and s2 and z1 and s0) or
          (s7 and z6 and s5               and s2        and s0) or
          (s7 and z6 and s5               and s2 and s1       ) or
          (s7 and z6 and s5 and z4 and z3               and s0) or
          (s7 and z6 and s5 and z4 and z3        and s1       ) or
          (s7 and s6 and s5 and s4 and s3 and z2 and z1       ) ;
h2kbsu := (z7 and s6 and z5 and s4 and z3 and s2 and z1       ) or
          (z7 and s6 and z5 and s4 and z3 and s2        and z0) or
          (z7 and s6 and z5 and s4 and s3 and z2 and z1       ) or
          (z7 and s6 and z5 and s4 and z3 and s2 and s1 and s0 and cc2z) ;
h1kasu := (s7 and z6 and z5 and z4 and z3 and z2 and s1       ) or
          (s7 and z6 and z5 and z4 and z3 and z2        and s0) or
          (s7 and s6 and s5 and s4        and s2 and z1       ) ;
h2kasu := (z7 and s6 and s5               and z2 and s1       ) or
          (z7 and s6 and s5               and z2        and s0) or
          (z7 and s6 and s5 and z4 and z3 and z2              ) ;

f1xsu  := (z7 and z6        and z4 and s3                     ) ;
f1ysu  := (z7 and z6        and s4 and z3                     ) ;
f1zsu  := (z7 and z6        and s4 and s3                     ) ;
f2xsu  := (z7 and s6 and z5 and s4 and s3 and z2 and s1       ) ;
f2ysu  := (z7 and s6 and z5 and s4 and s3 and s2 and z1       ) ;
f2zsu  := (z7 and s6 and z5 and s4 and s3 and s2 and s1       ) ;
f1xab  := (z7 and z6        and z4 and z3 and z2 and s1       ) or
          (s7 and z6 and s5 and z4 and s3 and z2 and z1       ) ;
f1yab  := (z7 and z6        and z4 and z3 and s2 and z1       ) or
          (s7 and z6 and s5 and s4 and z3 and z2 and z1       ) ;
f1zab  := (z7 and z6        and z4 and z3 and s2 and s1       ) or
          (s7 and z6 and s5 and s4 and s3 and z2 and z1       ) ;
f1xdc  := (s7 and s6 and z5        and s3 and z2 and s1 and s0 and cccs) ;
f1ydc  := (s7 and s6 and z5        and s3 and s2 and z1 and s0 and cccs) ;
f1zdc  := (s7 and s6 and z5        and s3 and s2 and s1 and s0 and cccs) ;
f1xic  := (s7 and s6 and z5        and s3 and z2 and s1 and z0 and cccs) ;
f1yic  := (s7 and s6 and z5        and s3 and s2 and z1 and z0 and cccs) ;
f1zic  := (s7 and s6 and z5        and s3 and s2 and s1 and z0 and cccs) ;

f1kaw  <= (s7 and s6 and s5 and z4 and z3 and s2        and z0) or
          (s7 and s6 and s5 and z4 and z3 and s2 and z1       ) ;
f1kaa  <= (s7 and s6 and z5 and s4 and s3        and s1       ) or
          (s7 and s6 and z5 and s4 and s3 and s2              ) or
          (s7 and s6 and s5 and z4        and z2 and s1       ) or
          (s7 and s6 and s5        and z3 and z2 and s1       ) or
          (s7 and s6 and s5 and z4 and s3        and s1 and s0) or
          (s7 and z6 and z5 and z4 and s3                     ) or
          (s7 and z6 and z5 and z4 and z3 and s2 and z1 and z0) ;
f2kaa  <= (z7 and s6 and s5               and s2 and z1 and z0) ;
f1kbb  <= (s7 and s6 and z5 and s4 and s3        and s1       ) or
          (s7 and s6 and z5 and s4 and s3 and s2              ) or
          (s7 and s6 and s5 and z4        and z2 and z1       ) or
          (s7 and s6 and s5        and z3 and z2 and z1       ) ;
f1kac  <= (s7 and z6 and s5                      and z1 and z0) or
          (s7 and z6 and z5 and s4 and z3                     ) or
          (s7 and s6 and s5 and s4 and s3        and s1       ) or
          (s7 and s6 and z5 and s4 and z3               and z0) ;
f1kbd  <= (s7 and z6 and s5                      and z1 and z0) or
          (s7 and z6 and z5 and s4 and z3                     ) or
          (s7 and s6 and s5 and s4 and s3        and s1       ) ;
f1kad  <= (s7 and z6 and z5 and s4 and s3                     ) or
          (s7 and s6 and z5 and s4 and z3               and s0) ;
f1kbc  <= (s7 and z6 and z5 and s4 and s3                     ) or
          (s7 and z6 and z5 and z4        and z2 and z1 and z0) ;

f1kasu <= h1kasu or h1kbsu ;
f2kasu <= h2kasu or h2kbsu ;
f1kbsu <= h1kbsu ;
f2kbsu <= h2kbsu ;

f1kant <= (s7 and z6 and z5 and z4 and z3 and s2        and s0) ;
f2kant <= (z7 and s6 and s5               and s2        and s0) ;
f1kaxr <= (s7 and z6 and z5 and z4 and z3 and s2 and s1 and z0) ;
f2kaxr <= (z7 and s6 and s5               and s2 and s1 and z0) ;

f1qcd  <= (s7 and s6 and s5 and s4 and s3 and s2 and s1 and s0) ;

f1vw   <= (z7 and s6 and z5 and z4 and z3 and z2              ) or
          (s7 and s6 and z5 and z4 and z3 and z2 and z1       ) or
          (s7 and s6 and s5 and z4 and z3 and z2        and z0) or
          (s7 and s6 and s5 and z4        and s2 and s1 and s0) or
          (s7 and s6 and s5 and z4 and s3                     ) ;
f1vcy  <= (s7 and s6 and s5 and s4 and z3 and s2 and z1 and z0) or
          (s7 and z6        and z4 and z3 and z2 and s1 and z0) ;
f2vcy  <= (z7 and s6 and s5               and z2 and s1 and z0) ;
f1vcn  <= (s7 and s6 and s5 and s4 and z3 and s2 and z1 and s0) or
          (s7 and z6        and z4 and z3 and z2        and s0) ;
f2vcn  <= (z7 and s6 and s5               and z2        and s0) ;
f1vnz  <= (s7 and s6 and s5 and z4 and z3 and z2        and s0) ;

f1xzsu <= f1xsu or f1ysu or f1zsu;
f2xzsu <= f2xsu or f2ysu or f2zsu;
f1xzab <= f1xab or f1yab or f1zab;
f1xzdc <= f1xdc or f1ydc or f1zdc;
f1xzic <= f1xic or f1yic or f1zic;

f1wx   <= f1xsu or f1xab or f1xdc or f1xic;
f2wx   <= f2xsu;
f1wy   <= f1ysu or f1yab or f1ydc or f1yic;
f2wy   <= f2ysu;
f1wz   <= f1zsu or f1zab or f1zdc or f1zic;
f2wz   <= f2zsu;

f1ssab <= (z7 and z6        and z4 and z3 and z2 and z1       ) or
          (s7 and z6 and s5 and z4 and z3 and z2 and z1 and z0) ;
f1ssda <= (s7 and s6 and z5 and s4 and s3 and z2 and z1 and s0) or
          (s7 and s6 and z5 and z4 and s3                      and cccs) ;
f3ssda <= (z7 and s6 and z5 and s4 and z3 and z2 and s1 and s0) ;
f1ssia <= (s7 and s6 and z5 and s4 and s3 and z2 and z1 and z0) ;
f1sscd <= (s7 and z6 and s5        and s3 and z2        and s0) or
          (s7 and z6 and s5 and s4        and z2        and s0) ;

f1psu  <= (z7 and s6 and z5                      and s1        and cccs) ;
f2psu  <= (z7 and s6 and z5                                    and cccs) ;
f1pin  <= not (
          (z7 and s6 and z5                      and s1        and cccs) or
          (z7 and s6 and s5        and s3                     ) or
          (z7 and s6 and s5 and s4                            ) or
          (s7 and s6 and s5 and s4 and z3 and s2 and s1 and z0));

f1rn   <= (s7 and s6 and s5 and s4        and s2 and s1 and s0) ;
f2rn   <= (z7 and s6 and z5 and s4 and z3 and z2 and z1 and s0) ;

f1opa  <= not (
          (z7 and s6                                          ) or
          (s7 and s6 and s5 and s4 and z3 and s2 and s1 and z0));

f1opz  <= (z7 and z6 and z5 and z4 and z3 and z2 and z1 and z0) ;

f1sef  <= not (
          (z7 and s6                                          ) or
          (s7 and s6 and s5 and s4 and z3 and s2 and s1 and z0) or
          (z7 and z6 and z5 and z4 and z3 and z2 and z1 and z0));
f2sef  <= not (
          (z7 and s6 and z5                                    and cccs) or
          (z7 and s6 and z5 and s4 and z3 and s2 and s1 and s0 and cc2s));
f3sef  <= not
          (z7 and s6 and z5 and s4 and z3 and s2 and s1 and s0 and cc2s) ;

f1sn2  <= (s7 and z6 and s5 and s4        and z2 and s1 and z0) or
          (s7 and z6 and s5        and s3 and z2 and s1 and z0) or
          (z7 and z6 and z5 and z4 and z3 and z2 and z1 and z0) ;
f1sn1  <= (s7 and z6 and s5 and s4        and z2 and s1 and z0) ;
f1sn0  <= (s7 and z6 and s5        and s3 and z2 and s1 and z0) ;

end process elementeb;
----------------------
writeq : process(clk) begin

  if clk'event and clk = '1' then if ena = '1' then

  q1kaw  <= f1kaw ;  q1kaa  <= f1kaa ;  q2kaa  <= f2kaa ;  q1kbb  <= f1kbb ;
  q1kac  <= f1kac ;  q1kbd  <= f1kbd ;  q1kad  <= f1kad ;  q1kbc  <= f1kbc ;
  q1kasu <= f1kasu;  q2kasu <= f2kasu;  q1kbsu <= f1kbsu;  q2kbsu <= f2kbsu;
  q1kant <= f1kant;  q2kant <= f2kant;  q1kaxr <= f1kaxr;  q2kaxr <= f2kaxr;
  q1qcd  <= f1qcd ;  q1vw   <= f1vw  ;  q1vcy  <= f1vcy ;  q2vcy  <= f2vcy ;
  q1vcn  <= f1vcn ;  q2vcn  <= f2vcn ;  q1vnz  <= f1vnz ;  q1xzsu <= f1xzsu;
  q2xzsu <= f2xzsu;  q1xzab <= f1xzab;  q1xzdc <= f1xzdc;  q1xzic <= f1xzic;
  q1wx   <= f1wx  ;  q2wx   <= f2wx  ;  q1wy   <= f1wy  ;  q2wy   <= f2wy  ;
  q1wz   <= f1wz  ;  q2wz   <= f2wz  ;  q1ssab <= f1ssab;  q1ssda <= f1ssda;
  q3ssda <= f3ssda;  q1ssia <= f1ssia;  q1sscd <= f1sscd;  q1pin  <= f1pin ;
  q1psu  <= f1psu ;  q2psu  <= f2psu ;  q1rn   <= f1rn  ;  q2rn   <= f2rn  ;
  q1opa  <= f1opa ;  q1opz  <= f1opz ;  q1sef  <= f1sef ;  q2sef  <= f2sef ;
  q3sef  <= f3sef ;  q1sn2  <= f1sn2 ;  q1sn1  <= f1sn1 ;  q1sn0  <= f1sn0 ;

end if; end if; end process writeq;
-----------------------------------

  wpp   <= (q1b and (q1pin or q1psu)) or
           (q2b and (q2sef or q2psu)) or (q3b and q3sef);

  epsum <= (q1b and q1psu) or (q2b and q2psu);

  wrr   <= (q1b and q1rn)  or (q2b and q2rn) or q4b;
  wqq   <=  q1b and q1qcd;

  wopa  <= act and ((q1b and q1opa) or (q2b and q2sef) or (q3b and q3sef));

  wvv   <= (q1b and (q1vcy  or q1vcn or q1vw or q1vnz)) or
           (q2b and (q2vcy  or q2vcn));

  evvw  <=  q1b and q1vw ;
  evvzo <=  q1b and q1vnz;
  evvcy <= (q1b and q1vcy)  or (q2b and q2vcy);
  evvcn <= (q1b and q1vcn)  or (q2b and q2vcn);

  wka   <= (q1b and (q1kaa  or q1kac  or q1kad or q1kasu  or
                     q1kant or q1kaxr or q1kaw))          or
           (q2b and (q2kant or q2kaxr or q2kaa or q2kasu));

  ekaa  <= (q1b and q1kaa)  or (q2b and q2kaa);
  ekac  <=  q1b and q1kac;
  ekad  <=  q1b and q1kad;
  ekasu <= (q1b and q1kasu) or (q2b and q2kasu);
  ekant <= (q1b and q1kant) or (q2b and q2kant);
  ekaxr <= (q1b and q1kaxr) or (q2b and q2kaxr);
  ekaw  <=  q1b and q1kaw;
  wkb   <= (q1b and (q1kbb  or q1kbc or q1kbd or q1kbsu)) or (q2b and q2kbsu);
  ekbb  <=  q1b and q1kbb;
  ekbc  <=  q1b and q1kbc;
  ekbd  <=  q1b and q1kbd;
  ekbsu <= (q1b and q1kbsu) or (q2b and q2kbsu);

  wss    <= (q1b and (q1ssda or q1ssia or q1ssab or q1sscd)) or
            (q3b and q3ssda);
  essdab <= (q1b and q1ssda) or (q3b and  q3ssda);
  essiab <=  q1b and q1ssia;
  essab  <=  q1b and q1ssab;
  esscd  <=  q1b and q1sscd;

  wxx    <= (q1b and q1wx)   or (q2b and q2wx);
  wyy    <= (q1b and q1wy)   or (q2b and q2wy);
  wzz    <= (q1b and q1wz)   or (q2b and q2wz);
  exztab <=  q1b and q1xzab;
  exzdcd <=  q1b and q1xzdc;
  exzicd <=  q1b and q1xzic;
  exzsum <= (q1b and q1xzsu) or (q2b and q2xzsu);

--end steub;
-------------------------------------------------------------------------------

  en3 <=  act and (p1a or p2a or p3a or p5a);

  en2 <=  act and ((p1a and p1sn2) or (p2a and p2sn2) or
                   (p3a and p3sn2) or (q1b and q1sn2) or qkb);

  en1 <=  act and ((p1a and p1sn1) or (q1b and q1sn1) or pha);

  en0 <= (act and ((p1a and p1sn0) or (q1b and q1sn0) or (pha and phsn0))) or
             (not act and (p1a or p2a or p3a or pha));

-------------------------------------------------------------------------------
end behcpu;
-------------------------------------------------------------------------------
