cpldfit: version J.33 Xilinx Inc. Fitter Report Design Name: test Date: 1-12-2011, 11:17PM Device Used: XC95288XL-6-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 28 /288 ( 10%) 27 /1440 ( 2%) 60 /864 ( 7%) 28 /288 ( 10%) 4 /117 ( 3%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 8/18 7/54 7/90 0/ 8 FB2 0/18 0/54 0/90 0/10 FB3 18/18* 26/54 18/90 1/ 5 FB4 0/18 0/54 0/90 0/ 6 FB5 2/18 27/54 2/90 2/ 8 FB6 0/18 0/54 0/90 0/ 8 FB7 0/18 0/54 0/90 0/ 4 FB8 0/18 0/54 0/90 0/ 5 FB9 0/18 0/54 0/90 0/ 9 FB10 0/18 0/54 0/90 0/10 FB11 0/18 0/54 0/90 0/ 7 FB12 0/18 0/54 0/90 0/ 6 FB13 0/18 0/54 0/90 0/ 6 FB14 0/18 0/54 0/90 0/ 8 FB15 0/18 0/54 0/90 0/ 9 FB16 0/18 0/54 0/90 0/ 8 ----- ----- ----- ----- 28/288 60/864 27/1440 3/117 * - Resource is exhausted ** Global Control Resources ** Signal 'clk' mapped onto global clock net GCK2. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 0 0 | I/O : 3 109 Output : 3 3 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 0 4 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 4 4 ** Power Data ** There are 28 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 3 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State led1 1 23 FB3_15 33 I/O O STD FAST RESET led2 1 25 FB5_2 34 I/O O STD FAST RESET led3 1 27 FB5_5 35 I/O O STD FAST RESET ** 25 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State cnt<7> 1 7 FB1_11 STD RESET cnt<6> 1 6 FB1_12 STD RESET cnt<5> 1 5 FB1_13 STD RESET cnt<4> 1 4 FB1_14 STD RESET cnt<3> 1 3 FB1_15 STD RESET cnt<2> 1 2 FB1_16 STD RESET cnt<1> 1 1 FB1_17 STD RESET cnt<0> 0 0 FB1_18 STD RESET cnt<9> 1 9 FB3_1 STD RESET cnt<8> 1 8 FB3_2 STD RESET cnt<26> 1 26 FB3_3 STD RESET cnt<24> 1 24 FB3_4 STD RESET cnt<22> 1 22 FB3_5 STD RESET cnt<21> 1 21 FB3_6 STD RESET cnt<20> 1 20 FB3_7 STD RESET cnt<19> 1 19 FB3_8 STD RESET cnt<18> 1 18 FB3_9 STD RESET cnt<17> 1 17 FB3_10 STD RESET cnt<16> 1 16 FB3_11 STD RESET cnt<15> 1 15 FB3_12 STD RESET cnt<14> 1 14 FB3_13 STD RESET cnt<13> 1 13 FB3_14 STD RESET cnt<12> 1 12 FB3_16 STD RESET cnt<11> 1 11 FB3_17 STD RESET cnt<10> 1 10 FB3_18 STD RESET ** 1 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use clk FB3_14 32 GCK/I/O GCK Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 7/47 Number of signals used by logic mapping into function block: 7 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 (b) (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 20 I/O (unused) 0 0 0 5 FB1_6 21 I/O (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 22 I/O (unused) 0 0 0 5 FB1_9 (b) (unused) 0 0 0 5 FB1_10 23 I/O cnt<7> 1 0 0 4 FB1_11 (b) (b) cnt<6> 1 0 0 4 FB1_12 24 I/O (b) cnt<5> 1 0 0 4 FB1_13 (b) (b) cnt<4> 1 0 0 4 FB1_14 25 I/O (b) cnt<3> 1 0 0 4 FB1_15 26 I/O (b) cnt<2> 1 0 0 4 FB1_16 (b) (b) cnt<1> 1 0 0 4 FB1_17 27 I/O (b) cnt<0> 0 0 0 5 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: cnt<0> 4: cnt<3> 6: cnt<5> 2: cnt<1> 5: cnt<4> 7: cnt<6> 3: cnt<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs cnt<7> XXXXXXX................................. 7 cnt<6> XXXXXX.................................. 6 cnt<5> XXXXX................................... 5 cnt<4> XXXX.................................... 4 cnt<3> XXX..................................... 3 cnt<2> XX...................................... 2 cnt<1> X....................................... 1 cnt<0> ........................................ 0 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 9 I/O (unused) 0 0 0 5 FB2_3 10 I/O (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 11 I/O (unused) 0 0 0 5 FB2_6 12 I/O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 13 I/O (unused) 0 0 0 5 FB2_9 (b) (unused) 0 0 0 5 FB2_10 14 I/O (unused) 0 0 0 5 FB2_11 (b) (unused) 0 0 0 5 FB2_12 15 I/O (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 16 I/O (unused) 0 0 0 5 FB2_15 17 I/O (unused) 0 0 0 5 FB2_16 (b) (unused) 0 0 0 5 FB2_17 19 I/O (unused) 0 0 0 5 FB2_18 (b) *********************************** FB3 *********************************** Number of function block inputs used/remaining: 26/28 Number of signals used by logic mapping into function block: 26 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use cnt<9> 1 0 0 4 FB3_1 (b) (b) cnt<8> 1 0 0 4 FB3_2 28 I/O (b) cnt<26> 1 0 0 4 FB3_3 (b) (b) cnt<24> 1 0 0 4 FB3_4 (b) (b) cnt<22> 1 0 0 4 FB3_5 (b) (b) cnt<21> 1 0 0 4 FB3_6 (b) (b) cnt<20> 1 0 0 4 FB3_7 (b) (b) cnt<19> 1 0 0 4 FB3_8 (b) (b) cnt<18> 1 0 0 4 FB3_9 (b) (b) cnt<17> 1 0 0 4 FB3_10 30 GCK/I/O (b) cnt<16> 1 0 0 4 FB3_11 (b) (b) cnt<15> 1 0 0 4 FB3_12 31 I/O (b) cnt<14> 1 0 0 4 FB3_13 (b) (b) cnt<13> 1 0 0 4 FB3_14 32 GCK/I/O GCK led1 1 0 0 4 FB3_15 33 I/O O cnt<12> 1 0 0 4 FB3_16 (b) (b) cnt<11> 1 0 0 4 FB3_17 (b) (b) cnt<10> 1 0 0 4 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: cnt<0> 10: cnt<18> 19: cnt<4> 2: cnt<10> 11: cnt<19> 20: cnt<5> 3: cnt<11> 12: cnt<1> 21: cnt<6> 4: cnt<12> 13: cnt<20> 22: cnt<7> 5: cnt<13> 14: cnt<21> 23: cnt<8> 6: cnt<14> 15: cnt<22> 24: cnt<9> 7: cnt<15> 16: cnt<24> 25: led1 8: cnt<16> 17: cnt<2> 26: led2 9: cnt<17> 18: cnt<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs cnt<9> X..........X....XXXXXXX................. 9 cnt<8> X..........X....XXXXXX.................. 8 cnt<26> XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 26 cnt<24> XXXXXXXXXXXXXXX.XXXXXXXXX............... 24 cnt<22> XXXXXXXXXXXXXX..XXXXXXXX................ 22 cnt<21> XXXXXXXXXXXXX...XXXXXXXX................ 21 cnt<20> XXXXXXXXXXXX....XXXXXXXX................ 20 cnt<19> XXXXXXXXXX.X....XXXXXXXX................ 19 cnt<18> XXXXXXXXX..X....XXXXXXXX................ 18 cnt<17> XXXXXXXX...X....XXXXXXXX................ 17 cnt<16> XXXXXXX....X....XXXXXXXX................ 16 cnt<15> XXXXXX.....X....XXXXXXXX................ 15 cnt<14> XXXXX......X....XXXXXXXX................ 14 cnt<13> XXXX.......X....XXXXXXXX................ 13 led1 XXXXXXXXXXXXXXX.XXXXXXXX................ 23 cnt<12> XXX........X....XXXXXXXX................ 12 cnt<11> XX.........X....XXXXXXXX................ 11 cnt<10> X..........X....XXXXXXXX................ 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 2 GTS/I/O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 3 GTS/I/O (unused) 0 0 0 5 FB4_6 4 I/O (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 5 GTS/I/O (unused) 0 0 0 5 FB4_9 (b) (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 (b) (unused) 0 0 0 5 FB4_12 6 GTS/I/O (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 7 I/O (unused) 0 0 0 5 FB4_15 (b) (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 (b) (unused) 0 0 0 5 FB4_18 (b) *********************************** FB5 *********************************** Number of function block inputs used/remaining: 27/27 Number of signals used by logic mapping into function block: 27 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB5_1 (b) led2 1 0 0 4 FB5_2 34 I/O O (unused) 0 0 0 5 FB5_3 (b) (unused) 0 0 0 5 FB5_4 (b) led3 1 0 0 4 FB5_5 35 I/O O (unused) 0 0 0 5 FB5_6 (b) (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 38 GCK/I/O (unused) 0 0 0 5 FB5_9 (b) (unused) 0 0 0 5 FB5_10 39 I/O (unused) 0 0 0 5 FB5_11 (b) (unused) 0 0 0 5 FB5_12 40 I/O (unused) 0 0 0 5 FB5_13 (b) (unused) 0 0 0 5 FB5_14 41 I/O (unused) 0 0 0 5 FB5_15 43 I/O (unused) 0 0 0 5 FB5_16 (b) (unused) 0 0 0 5 FB5_17 44 I/O (unused) 0 0 0 5 FB5_18 (b) Signals Used by Logic in Function Block 1: cnt<0> 10: cnt<18> 19: cnt<3> 2: cnt<10> 11: cnt<19> 20: cnt<4> 3: cnt<11> 12: cnt<1> 21: cnt<5> 4: cnt<12> 13: cnt<20> 22: cnt<6> 5: cnt<13> 14: cnt<21> 23: cnt<7> 6: cnt<14> 15: cnt<22> 24: cnt<8> 7: cnt<15> 16: cnt<24> 25: cnt<9> 8: cnt<16> 17: cnt<26> 26: led1 9: cnt<17> 18: cnt<2> 27: led2 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs led2 XXXXXXXXXXXXXXXX.XXXXXXXXX.............. 25 led3 XXXXXXXXXXXXXXXXXXXXXXXXXXX............. 27 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) (unused) 0 0 0 5 FB6_2 135 I/O (unused) 0 0 0 5 FB6_3 136 I/O (unused) 0 0 0 5 FB6_4 (b) (unused) 0 0 0 5 FB6_5 137 I/O (unused) 0 0 0 5 FB6_6 138 I/O (unused) 0 0 0 5 FB6_7 (b) (unused) 0 0 0 5 FB6_8 139 I/O (unused) 0 0 0 5 FB6_9 (b) (unused) 0 0 0 5 FB6_10 140 I/O (unused) 0 0 0 5 FB6_11 (b) (unused) 0 0 0 5 FB6_12 (b) (unused) 0 0 0 5 FB6_13 (b) (unused) 0 0 0 5 FB6_14 142 I/O (unused) 0 0 0 5 FB6_15 143 GSR/I/O (unused) 0 0 0 5 FB6_16 (b) (unused) 0 0 0 5 FB6_17 (b) (unused) 0 0 0 5 FB6_18 (b) *********************************** FB7 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB7_1 (b) (unused) 0 0 0 5 FB7_2 (b) (unused) 0 0 0 5 FB7_3 45 I/O (unused) 0 0 0 5 FB7_4 (b) (unused) 0 0 0 5 FB7_5 46 I/O (unused) 0 0 0 5 FB7_6 (b) (unused) 0 0 0 5 FB7_7 (b) (unused) 0 0 0 5 FB7_8 (b) (unused) 0 0 0 5 FB7_9 (b) (unused) 0 0 0 5 FB7_10 (b) (unused) 0 0 0 5 FB7_11 (b) (unused) 0 0 0 5 FB7_12 48 I/O (unused) 0 0 0 5 FB7_13 (b) (unused) 0 0 0 5 FB7_14 (b) (unused) 0 0 0 5 FB7_15 49 I/O (unused) 0 0 0 5 FB7_16 (b) (unused) 0 0 0 5 FB7_17 (b) (unused) 0 0 0 5 FB7_18 (b) *********************************** FB8 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB8_1 (b) (unused) 0 0 0 5 FB8_2 130 I/O (unused) 0 0 0 5 FB8_3 131 I/O (unused) 0 0 0 5 FB8_4 (b) (unused) 0 0 0 5 FB8_5 132 I/O (unused) 0 0 0 5 FB8_6 (b) (unused) 0 0 0 5 FB8_7 (b) (unused) 0 0 0 5 FB8_8 133 I/O (unused) 0 0 0 5 FB8_9 (b) (unused) 0 0 0 5 FB8_10 134 I/O (unused) 0 0 0 5 FB8_11 (b) (unused) 0 0 0 5 FB8_12 (b) (unused) 0 0 0 5 FB8_13 (b) (unused) 0 0 0 5 FB8_14 (b) (unused) 0 0 0 5 FB8_15 (b) (unused) 0 0 0 5 FB8_16 (b) (unused) 0 0 0 5 FB8_17 (b) (unused) 0 0 0 5 FB8_18 (b) *********************************** FB9 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB9_1 (b) (unused) 0 0 0 5 FB9_2 50 I/O (unused) 0 0 0 5 FB9_3 51 I/O (unused) 0 0 0 5 FB9_4 (b) (unused) 0 0 0 5 FB9_5 52 I/O (unused) 0 0 0 5 FB9_6 53 I/O (unused) 0 0 0 5 FB9_7 (b) (unused) 0 0 0 5 FB9_8 54 I/O (unused) 0 0 0 5 FB9_9 (b) (unused) 0 0 0 5 FB9_10 (b) (unused) 0 0 0 5 FB9_11 56 I/O (unused) 0 0 0 5 FB9_12 57 I/O (unused) 0 0 0 5 FB9_13 (b) (unused) 0 0 0 5 FB9_14 58 I/O (unused) 0 0 0 5 FB9_15 (b) (unused) 0 0 0 5 FB9_16 (b) (unused) 0 0 0 5 FB9_17 59 I/O (unused) 0 0 0 5 FB9_18 (b) *********************************** FB10 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB10_1 (b) (unused) 0 0 0 5 FB10_2 117 I/O (unused) 0 0 0 5 FB10_3 118 I/O (unused) 0 0 0 5 FB10_4 (b) (unused) 0 0 0 5 FB10_5 119 I/O (unused) 0 0 0 5 FB10_6 120 I/O (unused) 0 0 0 5 FB10_7 (b) (unused) 0 0 0 5 FB10_8 121 I/O (unused) 0 0 0 5 FB10_9 (b) (unused) 0 0 0 5 FB10_10 124 I/O (unused) 0 0 0 5 FB10_11 125 I/O (unused) 0 0 0 5 FB10_12 126 I/O (unused) 0 0 0 5 FB10_13 (b) (unused) 0 0 0 5 FB10_14 128 I/O (unused) 0 0 0 5 FB10_15 (b) (unused) 0 0 0 5 FB10_16 (b) (unused) 0 0 0 5 FB10_17 129 I/O (unused) 0 0 0 5 FB10_18 (b) *********************************** FB11 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB11_1 (b) (unused) 0 0 0 5 FB11_2 (b) (unused) 0 0 0 5 FB11_3 60 I/O (unused) 0 0 0 5 FB11_4 (b) (unused) 0 0 0 5 FB11_5 61 I/O (unused) 0 0 0 5 FB11_6 (b) (unused) 0 0 0 5 FB11_7 (b) (unused) 0 0 0 5 FB11_8 (b) (unused) 0 0 0 5 FB11_9 (b) (unused) 0 0 0 5 FB11_10 64 I/O (unused) 0 0 0 5 FB11_11 66 I/O (unused) 0 0 0 5 FB11_12 68 I/O (unused) 0 0 0 5 FB11_13 (b) (unused) 0 0 0 5 FB11_14 69 I/O (unused) 0 0 0 5 FB11_15 (b) (unused) 0 0 0 5 FB11_16 (b) (unused) 0 0 0 5 FB11_17 70 I/O (unused) 0 0 0 5 FB11_18 (b) *********************************** FB12 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB12_1 (b) (unused) 0 0 0 5 FB12_2 110 I/O (unused) 0 0 0 5 FB12_3 111 I/O (unused) 0 0 0 5 FB12_4 (b) (unused) 0 0 0 5 FB12_5 112 I/O (unused) 0 0 0 5 FB12_6 (b) (unused) 0 0 0 5 FB12_7 (b) (unused) 0 0 0 5 FB12_8 113 I/O (unused) 0 0 0 5 FB12_9 (b) (unused) 0 0 0 5 FB12_10 115 I/O (unused) 0 0 0 5 FB12_11 (b) (unused) 0 0 0 5 FB12_12 116 I/O (unused) 0 0 0 5 FB12_13 (b) (unused) 0 0 0 5 FB12_14 (b) (unused) 0 0 0 5 FB12_15 (b) (unused) 0 0 0 5 FB12_16 (b) (unused) 0 0 0 5 FB12_17 (b) (unused) 0 0 0 5 FB12_18 (b) *********************************** FB13 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB13_1 (b) (unused) 0 0 0 5 FB13_2 71 I/O (unused) 0 0 0 5 FB13_3 (b) (unused) 0 0 0 5 FB13_4 (b) (unused) 0 0 0 5 FB13_5 (b) (unused) 0 0 0 5 FB13_6 (b) (unused) 0 0 0 5 FB13_7 (b) (unused) 0 0 0 5 FB13_8 74 I/O (unused) 0 0 0 5 FB13_9 (b) (unused) 0 0 0 5 FB13_10 (b) (unused) 0 0 0 5 FB13_11 75 I/O (unused) 0 0 0 5 FB13_12 (b) (unused) 0 0 0 5 FB13_13 (b) (unused) 0 0 0 5 FB13_14 76 I/O (unused) 0 0 0 5 FB13_15 77 I/O (unused) 0 0 0 5 FB13_16 (b) (unused) 0 0 0 5 FB13_17 78 I/O (unused) 0 0 0 5 FB13_18 (b) *********************************** FB14 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB14_1 (b) (unused) 0 0 0 5 FB14_2 (b) (unused) 0 0 0 5 FB14_3 100 I/O (unused) 0 0 0 5 FB14_4 (b) (unused) 0 0 0 5 FB14_5 101 I/O (unused) 0 0 0 5 FB14_6 102 I/O (unused) 0 0 0 5 FB14_7 (b) (unused) 0 0 0 5 FB14_8 103 I/O (unused) 0 0 0 5 FB14_9 (b) (unused) 0 0 0 5 FB14_10 104 I/O (unused) 0 0 0 5 FB14_11 105 I/O (unused) 0 0 0 5 FB14_12 (b) (unused) 0 0 0 5 FB14_13 (b) (unused) 0 0 0 5 FB14_14 106 I/O (unused) 0 0 0 5 FB14_15 107 I/O (unused) 0 0 0 5 FB14_16 (b) (unused) 0 0 0 5 FB14_17 (b) (unused) 0 0 0 5 FB14_18 (b) *********************************** FB15 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB15_1 (b) (unused) 0 0 0 5 FB15_2 79 I/O (unused) 0 0 0 5 FB15_3 80 I/O (unused) 0 0 0 5 FB15_4 (b) (unused) 0 0 0 5 FB15_5 (b) (unused) 0 0 0 5 FB15_6 (b) (unused) 0 0 0 5 FB15_7 (b) (unused) 0 0 0 5 FB15_8 81 I/O (unused) 0 0 0 5 FB15_9 (b) (unused) 0 0 0 5 FB15_10 82 I/O (unused) 0 0 0 5 FB15_11 83 I/O (unused) 0 0 0 5 FB15_12 85 I/O (unused) 0 0 0 5 FB15_13 (b) (unused) 0 0 0 5 FB15_14 86 I/O (unused) 0 0 0 5 FB15_15 87 I/O (unused) 0 0 0 5 FB15_16 (b) (unused) 0 0 0 5 FB15_17 88 I/O (unused) 0 0 0 5 FB15_18 (b) *********************************** FB16 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB16_1 (b) (unused) 0 0 0 5 FB16_2 91 I/O (unused) 0 0 0 5 FB16_3 92 I/O (unused) 0 0 0 5 FB16_4 (b) (unused) 0 0 0 5 FB16_5 93 I/O (unused) 0 0 0 5 FB16_6 94 I/O (unused) 0 0 0 5 FB16_7 (b) (unused) 0 0 0 5 FB16_8 95 I/O (unused) 0 0 0 5 FB16_9 (b) (unused) 0 0 0 5 FB16_10 96 I/O (unused) 0 0 0 5 FB16_11 97 I/O (unused) 0 0 0 5 FB16_12 98 I/O (unused) 0 0 0 5 FB16_13 (b) (unused) 0 0 0 5 FB16_14 (b) (unused) 0 0 0 5 FB16_15 (b) (unused) 0 0 0 5 FB16_16 (b) (unused) 0 0 0 5 FB16_17 (b) (unused) 0 0 0 5 FB16_18 (b) ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_cnt0: FTCPE port map (cnt(0),'1',clk,'0','0'); FTCPE_cnt1: FTCPE port map (cnt(1),cnt(0),clk,'0','0'); FTCPE_cnt2: FTCPE port map (cnt(2),cnt_T(2),clk,'0','0'); cnt_T(2) <= (cnt(0) AND cnt(1)); FTCPE_cnt3: FTCPE port map (cnt(3),cnt_T(3),clk,'0','0'); cnt_T(3) <= (cnt(0) AND cnt(1) AND cnt(2)); FTCPE_cnt4: FTCPE port map (cnt(4),cnt_T(4),clk,'0','0'); cnt_T(4) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3)); FTCPE_cnt5: FTCPE port map (cnt(5),cnt_T(5),clk,'0','0'); cnt_T(5) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4)); FTCPE_cnt6: FTCPE port map (cnt(6),cnt_T(6),clk,'0','0'); cnt_T(6) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5)); FTCPE_cnt7: FTCPE port map (cnt(7),cnt_T(7),clk,'0','0'); cnt_T(7) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6)); FTCPE_cnt8: FTCPE port map (cnt(8),cnt_T(8),clk,'0','0'); cnt_T(8) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7)); FTCPE_cnt9: FTCPE port map (cnt(9),cnt_T(9),clk,'0','0'); cnt_T(9) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8)); FTCPE_cnt10: FTCPE port map (cnt(10),cnt_T(10),clk,'0','0'); cnt_T(10) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt11: FTCPE port map (cnt(11),cnt_T(11),clk,'0','0'); cnt_T(11) <= (cnt(0) AND cnt(10) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt12: FTCPE port map (cnt(12),cnt_T(12),clk,'0','0'); cnt_T(12) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt13: FTCPE port map (cnt(13),cnt_T(13),clk,'0','0'); cnt_T(13) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt14: FTCPE port map (cnt(14),cnt_T(14),clk,'0','0'); cnt_T(14) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt15: FTCPE port map (cnt(15),cnt_T(15),clk,'0','0'); cnt_T(15) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt16: FTCPE port map (cnt(16),cnt_T(16),clk,'0','0'); cnt_T(16) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt17: FTCPE port map (cnt(17),cnt_T(17),clk,'0','0'); cnt_T(17) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt18: FTCPE port map (cnt(18),cnt_T(18),clk,'0','0'); cnt_T(18) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt19: FTCPE port map (cnt(19),cnt_T(19),clk,'0','0'); cnt_T(19) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt20: FTCPE port map (cnt(20),cnt_T(20),clk,'0','0'); cnt_T(20) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND cnt(19) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt21: FTCPE port map (cnt(21),cnt_T(21),clk,'0','0'); cnt_T(21) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt22: FTCPE port map (cnt(22),cnt_T(22),clk,'0','0'); cnt_T(22) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt24: FTCPE port map (cnt(24),cnt_T(24),clk,'0','0'); cnt_T(24) <= (led1 AND cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND cnt(22) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_cnt26: FTCPE port map (cnt(26),cnt_T(26),clk,'0','0'); cnt_T(26) <= (led1 AND led2 AND cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND cnt(22) AND cnt(24) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_led1: FTCPE port map (led1,led1_T,clk,'0','0'); led1_T <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND cnt(22) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_led2: FTCPE port map (led2,led2_T,clk,'0','0'); led2_T <= (led1 AND cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND cnt(22) AND cnt(24) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); FTCPE_led3: FTCPE port map (led3,led3_T,clk,'0','0'); led3_T <= (led1 AND led2 AND cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND cnt(22) AND cnt(24) AND cnt(26) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95288XL-6-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCC 2 KPR 74 KPR 3 KPR 75 KPR 4 KPR 76 KPR 5 KPR 77 KPR 6 KPR 78 KPR 7 KPR 79 KPR 8 VCC 80 KPR 9 KPR 81 KPR 10 KPR 82 KPR 11 KPR 83 KPR 12 KPR 84 VCC 13 KPR 85 KPR 14 KPR 86 KPR 15 KPR 87 KPR 16 KPR 88 KPR 17 KPR 89 GND 18 GND 90 GND 19 KPR 91 KPR 20 KPR 92 KPR 21 KPR 93 KPR 22 KPR 94 KPR 23 KPR 95 KPR 24 KPR 96 KPR 25 KPR 97 KPR 26 KPR 98 KPR 27 KPR 99 GND 28 KPR 100 KPR 29 GND 101 KPR 30 KPR 102 KPR 31 KPR 103 KPR 32 clk 104 KPR 33 led1 105 KPR 34 led2 106 KPR 35 led3 107 KPR 36 GND 108 GND 37 VCC 109 VCC 38 KPR 110 KPR 39 KPR 111 KPR 40 KPR 112 KPR 41 KPR 113 KPR 42 VCC 114 GND 43 KPR 115 KPR 44 KPR 116 KPR 45 KPR 117 KPR 46 KPR 118 KPR 47 GND 119 KPR 48 KPR 120 KPR 49 KPR 121 KPR 50 KPR 122 TDO 51 KPR 123 GND 52 KPR 124 KPR 53 KPR 125 KPR 54 KPR 126 KPR 55 VCC 127 VCC 56 KPR 128 KPR 57 KPR 129 KPR 58 KPR 130 KPR 59 KPR 131 KPR 60 KPR 132 KPR 61 KPR 133 KPR 62 GND 134 KPR 63 TDI 135 KPR 64 KPR 136 KPR 65 TMS 137 KPR 66 KPR 138 KPR 67 TCK 139 KPR 68 KPR 140 KPR 69 KPR 141 VCC 70 KPR 142 KPR 71 KPR 143 KPR 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95288xl-6-TQ144 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25