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Forum: FPGA, VHDL & Verilog How to output ROM data that is loaded from an MIF file on GTKwave?


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von Mahmoud R. (mahmoud899)


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I am writing a ROM vhdl code and I loaded the ROM with an MIF file. I 
wrote a testbench for the ROM and I ran it on GTKWave and there was no 
output when specific ROM addresses were selected.

ROM Code (rom.vhdl):
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity rom is
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generic(
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    addr_width  : integer := 16;
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    addr_bits   : integer := 4;
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    data_width  : integer := 8  
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);
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port(
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    address     : in std_logic_vector(addr_bits-1 downto 0);
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    dataout     : out std_logic_vector(data_width-1 downto 0)
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);
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end rom;
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architecture behavioral of rom is
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    type rom_type is array (0 to addr_width-1) of std_logic_vector(data_width-1 downto 0);
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    signal my_rom : rom_type;
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    -- note that 'ram_init_file' is not the user-defined-name (it is attribute name)
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    attribute ram_init_file : string;
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    -- "seven_seg_data.mif" is saved in the folder "ROM", then use "ROM/seven_seg_data.mif"
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    attribute ram_init_file of my_rom : signal is "romdata.mif";
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 begin
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    dataout <= my_rom(to_integer(unsigned(address)));
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 end behavioral;

ROM Testbench Code (rom_tb.vhdl):
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity rom_tb is
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end entity;
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architecture behavioral of rom_tb is
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component rom
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port(
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    address     : in std_logic_vector(3 downto 0);
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    dataout     : out std_logic_vector(7 downto 0)
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);
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end component;
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signal address  : std_logic_vector(3 downto 0);
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signal dataout  : std_logic_vector(7 downto 0);
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begin
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    U0 : rom port map (address, dataout);
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    stim_process : process
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    begin
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        address <= "0000";
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        wait for 10 ns;
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        address <= "0001";
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        wait for 10 ns;
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        address <= "0010";
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        wait for 10 ns;
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        address <= "0011";
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        wait for 10 ns;
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        address <= "0100";
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        wait for 10 ns;
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        assert false report "Reached end of test";
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        wait;
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    end process;
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end behavioral;

MIF File (romdata.mif):
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% romdata.mif %
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% ROM data    %
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% data width and total data %
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width=7;    % number of bits in each data
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depth=16;   % total number of data (i.e. total address) %
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%
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    format of the data and address stored in this file
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    uns : unsigned, dec : decimal, hex : hexadecimal
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    bin : binary, oct : octal
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%
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address_radix=uns;  % address is unsigned-type %
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data_radix=bin; % data is binary-type %
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% ROM data %
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content begin
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    [0..15] : 0000000;
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    0 : 00000000;
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    1 : 00000001;
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    2 : 00000010;
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    3 : 00000011;
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    4 : 00000100;
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    5 : 00000101;
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    6 : 00000110;
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    7 : 00000111;
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    8 : 00001000;
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    9 : 00001001;
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    10 : 00001010;
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    11 : 00001011;
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    12 : 00001100;
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    13 : 00001101;
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    14 : 00001110;
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    15 : 00001111;
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end;

What is wrong with the code and what do I need to do to be able to 
output what is stored in the memory addresses?

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