I'm a VHDL Beginner , and just found DEEDS (Run's ok in linux wine) It's a Logic simulator , and VHDL code generator with a littlt MCU built in. http://www.esng.dibe.unige.it/Deeds/ Just tried the one attached (added the missing Assembler code, as its for learning) http://www.esng.dibe.unige.it/Deeds/LearningMaterials/LM/T110/110043_Byte_Generator_On_FPGA/Index.htm Orig code : http://www.esng.dibe.unige.it/Deeds/LearningMaterials/LM/T110/110043.zip Current projects: http://www.esng.dibe.unige.it/Deeds/LearningMaterials/IndexByTopic.htm It's clearly a learning tool , but quite fun to play with. I haven't tried it on "Silicon" as im in the summerhouse don't have any HW with me. Maybe Lothar (or another "guru" could have a look :-) The attached code contains the project, assembler and VHDL mfg Bingo
Hmmm ... Additional Info. The above attached VHDL isn't complete. I just tried the "Test on FPGA" , and that one generates full quartus projects , for either Altera DE1 or DE2 (attached). I justtried the DE2 , it can be syhthezised w. Quartus. So i guess it's mostly a Quartus tool (if you're a beginner, like me) Bingo
I have a $18 ALTERA-FPGA-Cyclone-II-EP2C5T144-Minimum-System-Development-Board http://www.ebay.com/itm/201070505640 I can get Quartus t build the DE1 procject with the above FPGA if i reduce the Ram from 32K to 8K.
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In : Microcomputer_Module.vhd Change the Ram_Array -- Memory Array Types --------------------------------------------------------------- type RAM_Array is array (0 to 8191) of std_logic_vector(7 downto 0); type ROM_Array is array (0 to 359) of std_logic_vector(7 downto 0); The MCU is apparently based on the T80 (Original file Name: "T80.vhd") -- This VHDL code describes the core of the DMC8 microprocessor, -- a modified and reduced version of the original Z80 microprocessor The first op is to load the stack START: LD SP,0FFFFh ;stack pointer initialization And ah there is 32K ROM & 32K RAM in the DCM8 uC , i expect the ram to start @32K. But i haven't got the VHDL knowledge to verify it. If the above is correct , this means i should loat the SP with 32K+8K-1 = 09FFFh Dammm ... Why didn't i bring my cheap fpga board with me :-( Well hope someone wants to "play along" /Bingo
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