Suchergebnisse für "when others"

Neue IDE und Programmiersprache zur FPGA Programmierung

WHEN 1200006 => i := i + 1; Thread13 := 0; Thread9 := 2; WHEN others => Thread13 := 0; END CASE; WHEN 4 => IF (BTN = '1') THEN ELSE Thread9 := 0; END IF; WHEN others => Thread9 := 0; END CASE; END IF; END PROCESS; [/code] (Im Moment gibt es mit der öffentlichen Version nen Problem bei "i := 0;", weil ein fix nach hinten losgegangen ist. Wird

FPGA, VHDL & Co. ·Leon B. ·03.03.2021 20:42 ·97 Antworten

Zwei Prozesse nutzen einen Vektor. Geht das so?

- reagiert auf ce (change encoder) und RESET begin -- bei RESET - clear (others => '0') setzt alle Ausgaben auf '0', ... if (RESET = '1') then -- ... clear (others => '1') setzt alle Ausgaben auf '1', mit dem Setzen ... t_cnt1 <= (others => '1'); --

begin -- Concurrent statt Prozess --> kurz und kompakt ;-) srGET0 <= srGET0(0) & GET0in when rising edge(clk); srGET1 <= srGET1(0) & GET1in when rising edge(clk); srGET2 <= srGET2(0) & GET2in when rising edge(clk); process begin wait until rising_edge(clk);

FPGA, VHDL & Co. ·Reinhard J. ·17.11.2014 22:07 ·51 Antworten

Implementierung einer Figur

es werden nämlich 3 Bits für die Zustände verwendet, 8 Zustände und nur 6 sind abgedeckt. Klar mit when others wird das gelöst, aber was hat dann die Beschränkung gebracht?

Synthesizer der Meinung ist auf one-hot zu kodieren hast Du 6 Bits und 58 ungültige Zustände. Da hilft auch when others nicht. Meine Zustände haben übrigens Namen: [vhdl] type state_t is (IDLE, DOSOMETHING, DOSOMETHINGOTHER, READY); [/vhdl] Finde ich besser als [vhdl] type s16_type is ( S1, S2,

FPGA, VHDL & Co. ·zakar95 ·02.11.2017 14:10 ·16 Antworten

Multi Source Fehler

mux : PROCESS (DATA_OUTA_RAM1, DATA_OUTA_RAM1, ramenable_int) BEGIN CASE ramenable_int IS WHEN "01" => DATA_OUTA <= DATA_OUTA_RAM1; WHEN "10" => DATA_OUTA <= DATA_OUTA_RAM2; WHEN OTHERS => DATA_OUTA <= (OTHERS => '0'); END CASE; END PROCESS mux; [/vhdl] T.M. =========

FPGA, VHDL & Co. ·Dirk ·07.08.2006 17:05 ·6 Antworten

Bidirektionale Pins in Quartus II (Altera)

data_bus <= "ZZZZZZZZ"; end if; end process; -- Richtungsumschaltung my_io <= my_register when my_dir='1' else "ZZZZZZZZ"; [/vhdl] So in etwa. MFG Falk

0); signal data_bus_out : std_logic_vector(7 downto 0); ... ... data_bus_io <= data_bus_out when (WR='0') and (ENA='1') else (others => 'Z'); data_bus_in <= data_bus_io when (WR='1') and (ENA='1') else (others => 'Z'); Jetzt muss du beide interne Signale mit deinem Kommunikationsmodul oder

FPGA, VHDL & Co. ·Tobias P. ·07.12.2007 19:57 ·13 Antworten

Dreieckgenerator programmieren

process(Takt) begin if (Takt ='1' and Takt'event) then case Counter_up_down is when 0 => Counter_up_down <= 1; when 1 => Counter_up_down <= 2; when 2 => Counter_up_down <= 3; when 253 => Counter_up_down <= 254; when 254 => Counter_up_down <= 255; when 255 => Counter_up_down <= 254; when 254 => Counter_up_down <= 253; when 253 => Counter_up_down <= 252; when 252 => Counter_up_down <= 251; end case;

FPGA, VHDL & Co. ·VHDL Anfänger ·05.09.2009 09:01 ·11 Antworten

Demux Optimierung möglich?

24) <= wdata; when "0100" => data(39 downto 32) <= wdata; when "0101" => data(47 downto 40) <= wdata; when "0110" => data(55 downto 48) <= wdata; when "0111" => data(63 downto

88) <= wdata; when "1100" => data(103 downto 96) <= wdata; when "1101" => data(111 downto 104) <= wdata; when "1110" => data(119 downto 112) <= wdata; when others => data(127 downto

FPGA, VHDL & Co. ·Martin ·23.08.2014 14:02 ·12 Antworten

Merkwürdige Quartus Optimierung

ieee.std_logic_1164.all; entity blinker is port( LEDG : buffer std_logic_vector(7 downto 0) := (others => '0'); LEDR : buffer std_logic_vector(9 downto 0) := (others => '1'); CLOCK_50 : in std_logic ); end entity blinker; architecture behav of blinker is begin process(CLOCK_50)

blinker; architecture behav of blinker is signal LEDRint : std_logic_vector(9 downto 0) := (others => '1'); signal LEDGint : std_logic_vector(7 downto 0) := (others => '0'); begin process(CLOCK_50) is variable count : integer := 0; begin if rising_edge(CLOCK_50) then count

FPGA, VHDL & Co. ·Andy L. ·06.11.2012 20:23 ·33 Antworten

VIVADO2014.4 VHDL 2008

'3' "10011001" when "0100", -- Ziffer '4' "01001001" when "0101", -- Ziffer '5' "01000000" when "0110", -- Ziffer '6' "00011111" when "0111", -- Ziffer

bis auf ein evtl. fehlendes "when others" für die nicht angegebenen Fälle sehe ich da aber auch keinen Fehler. Habe das "with select" auch schon selbst in der ISE verwendet. Schreib uns doch mal die Fehlermeldung die du bekommst

FPGA, VHDL & Co. ·Marco G. ·18.04.2015 18:45 ·7 Antworten

Wittig(welec) DSO W20xxA Open Source Firmware (Teil4) Gesperrt

I noticed when some values are below certain >> levels then zero is showed: >Hmmm, difficult. I think it is because of the interpolation. I will >check if it can be improved. You knew the job was difficult when

@Luc & all others >> When QM is on, changing Time Base sometimes get corruption on the screen >Yes I noticed this too and I'm searching for the reason. I hope I can >fix it soon. Unfortunately I wasn't able

Mikrocontroller und Digitale Elektronik ·Kurt B. ·16.10.2011 22:58 ·1093 Antworten

Kann ein Automat "abstürzen" ?

weggelassen) process (Takt) begin if Takt = '1' and Takt'event then case zustand is when a => blabla leds <= "001"; if irgendwas then zustand <= b; end if; when b => blabla leds <= "010"; if irgendwas then

Anweisung reinpacken - dann hast du auf jeden Fall alle möglichen Zustände abgedeckt: case bla is when a => when b => when c => when others => end case; Gruß, Thomas

FPGA, VHDL & Co. ·Hans ·14.09.2006 19:37 ·12 Antworten

Universeller VGA Controller

vertical_counter vertical_counter <= vertical_counter + 1; horizontal_counter <= (others => '0'); end if; -- Vertical Sync Sync Pulse Time = 521 Lines if (vertical_counter = vga_mode.vertical_sync_pulse_time) then vertical_counter <= (others => '0'

process (clock) is begin if rising_edge(clock) then case vgamodus is when vga480x640at60 => vga_mode <= vgamode480x640at60; when vga600x800at72 => vga_mode <= vgamode600x800at72; end case; end if; end process; end architecture rtl; [/vhdl]

FPGA, VHDL & Co. ·Hans-Werner ·24.02.2009 08:35 ·8 Antworten

Sinus Phasen Verschiebung

architecture Behavioral of Blinky_test is --signal counter : std_logic_vector(9 downto 0) := (others => '0'); signal clk : std_logic := '0'; signal clk_div2 : std_logic := '0'; signal position_sinus1 : integer range 0 to 249 := 0; signal triangle : std_logic_vector(11 downto 0) := (others => '

- to be testet with 10MHz or 10kHz; one sample needs falling and (!) rising edge --LED0 <= '1' when counter < "0111111111" else '0'; LED0 <= '1' when position_sinus1 < 125 else '0'; --LED1 <= clk_div2;--KEY1 and COMP_IN; Inst_key_debounce: key_debounce PORT MAP( clk => clk, reset

FPGA, VHDL & Co. ·otti ·30.03.2011 14:36 ·8 Antworten

Frage zu elsif

when others => null;-)

Matz K. schrieb im Beitrag #4193062: > when others => null;-) Nicht ganz, das würde zu einem case-Statement passen. In dem Fall wäre "else" das Zauberwort (oder Default-Zuweisungen für alle Signale vor dem if-Statement, um keine ungewollten

FPGA, VHDL & Co. ·Herbert ·10.07.2015 18:58 ·23 Antworten

Enhancing Code Efficiency in C++

can help the complier; provided the compiler allows contribution. The compiler is the key point when it comes to producing efficient code. Hence the place to go is the compiler.

program does not need to be slower and bulkier than a C program. Only use the handy language constructs when they are contributing for good.

Softwareentwicklung ·Greg B. ·21.05.2024 12:50 ·49 Antworten

Kleine Änderung und mein Design läuft nicht mehr :(

when "0000" => SOUND_A <= "00000000"; when "0001" => SOUND_A <= "00000001"; when "0010" => SOUND_A <= "00000010"; when "0011" => SOUND_A <= "00000011"; when "0100" => SOUND_A

<= "01011010"; when "1111" => SOUND_A <= "01111111"; when others => null; end case; end if; end process; Mix_A <= Volume_A(3 downto 0); A <= SOUND_A when (Osc_A = '1' and Enable(0) = '0') or (Period_N_Out

FPGA, VHDL & Co. ·neuling ·26.03.2008 21:19 ·5 Antworten

Ampelschaltung mit Coolrunner2

> dec_out <= "100"; when 6 => dec_out <= "110"; when 7 => dec_out <= "110"; when 8 => dec_out <= "001"; when 9 => dec_out <= "001"; when 10 => dec_out <= "001"; when 11 => dec_out <= "001"; when 12 => dec_out <= "001"; when 13 => dec_out <= "001"; when 14 => dec_out <= "001"; when 15 => dec_out <= "001"; when others => dec_out <= "010"; end case; end

FPGA, VHDL & Co. ·Tobias Reinhard ·10.01.2014 13:11 ·15 Antworten

Probleme mit Zähler

0 setzen; when 3 => -- nach dritter Taktflanke -- enb war 0, count muss immernoch 2 sein assert count = "010" report "enb test failed" severity failure; -------------

'; --dir low schalten (rueckwaerts) when 10 => -- nach [10] Taktflanke -- count muss nun 1->[5] sein (rueckwaerts) assert count = "101" report "ceil test failed" severity failure; when others

FPGA, VHDL & Co. ·Justus B. ·30.12.2023 17:11 ·1 Antworten

Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung

hphone_l <= line_in_l; hphone_r <= line_in_r; nur 0en an den Ausgang zu geben: hphone_l <= (others => '0'); hphone_r <= (others => '0'); --> man hört immer noch die Musik vom IPod über die angeschlossenen Kopfhörer. Sche

start_fs_tic_f) ) then --nxt_state <= s_read; end if; --***************************** when s_read => nxt_state <= s_idle; end case; end process calc_next_state; -- Auscodierung Ausgaenge; with nxt_state select d_out_reg_ready_f <= '1' when s_read, '0' when s_idle

FPGA, VHDL & Co. ·itse_me_mario ·02.02.2021 19:51 ·287 Antworten

vhdl kontrollstruktur case mit vektoren

sw0; vec(3) := clk; vec(4) := y1; vec(5) := sw1; case vec is when "--100" => y0 <= '1'; start <= '1'; when "--1-1" => start <= '0'; when "---1-" => y0 <= '0'; when "001--" => y0 <= '1'; start <= '1'; when "101--" => start

version of case which allows don't care behaviour, case?. Here is an example: case? sel is when "1---" => o <= "11"; when "-1--" => o <= "10"; when "--1-" => o <= "01"; when "---1" => o <= "00"; when others => null; end case; The comparison is carried

FPGA, VHDL & Co. ·mikrofriendly ·10.06.2010 09:11 ·8 Antworten

Automat-Anzeigemodul

-- FSM-process mux: process (dig0, dig1, dig2, dig3, cnt) begin case cnt is when "00" => e <= dig0; when "01" => e <= dig1; when "10" => e <= dig2; when "11" => e <= dig3; when others => e <= 0; end case; end process mux; enc:process(e) begin case e is when 1 => data_array(index)(6 downto 0) <= "0000000"; when 2 => data_array(index)(6 downto 0) <= "0000001"; ... when 128 => data_array(index)(6 downto 0) <= "1111111"

FPGA, VHDL & Co. ·Adrian ·09.07.2007 15:06 ·11 Antworten

Logisch High/Low/RTL_EQ/Latch

arbeiten architecture Behavior of shift_reg is signal QINT: STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); begin shift_reg: process (CLK, Reset) begin if Reset = '1' then Q <= (others => '0'); elsif CLK = '1' and CLK'event then QINT <= D & QINT(7 downto 1 ) ; Q <

-- 1 -- links .. rechts signal reg : std_logic_vector(7 downto 0):= (others=>'0'); : reg <= DATAIN & reg(7 downto 1) when rising_edge(clk); [/vhdl] Oder so was: [vhdl] -- 2 -- links .. rechts signal reg : std_logic_vector(0 to 7):= (others=>'

FPGA, VHDL & Co. ·Sin S. ·02.02.2021 07:40 ·11 Antworten

Fehlermeldung mit unsigned

"; when "0011" => Sieben_segment_Ausgang(7 downto 1) <= "0000110"; when "0100" => Sieben_segment_Ausgang(7 downto 1) <= "1001100"; when "0101" => Sieben_segment_Ausgang(7 downto 1) <= "0100100

"; when "1111" => Sieben_segment_Ausgang(7 downto 1) <= "0111000"; when others => Sieben_segment_Ausgang(7 downto 1) <= "0000000"; end case; end process; seg_out <= Sieben_Segment_ausgang

FPGA, VHDL & Co. ·Andreas Hutstein ·30.11.2007 22:34 ·11 Antworten

Komische Info von ISE

; when R6 => state <= R7; when R7 => state <= idle; when W1 => state <= W2; when W2 => UART_CS <= '1'; state <= W3; when W3 => state <= W4; when W4 => UART_WR <= '1'; state <= W5; when W5 => state <= W6; when W6 => state <= W7; when W7 => state <= idle; when others

FPGA, VHDL & Co. ·Christian Peters ·23.07.2007 12:54 ·7 Antworten

Uhr Beschreiben

--4 when "0101" => LED <="0010010"; --5 when "0110" => LED <="0000010"; --6 when "0111" => LED <="1111000"; --7 when "1000" => LED <="0000000"; --8 when "1001" => LED <="0010000"; --9 when others => LED <="0000110"; -- Error end case; end process; end Anzeige; [/vhdl]

FPGA, VHDL & Co. ·Flo ·07.03.2011 19:46 ·22 Antworten

Signal bleibt ständig undefiniert

normalerweise anders. Nämlich mit einer Typdefinition für die Zustände. Dann braucht man auch keinen /others/ Pfad: http://www.lothar-miller.de/s9y/archives/30-when-others.html Sparxx schrieb im Beitrag #2597797: > Das Signal musst du zuerst initialisieren,es kann ja nicht irgendeinen > Anfangswert

Übrigens das hier brauchst du nicht,glaube ich: [vhdl]WHEN state_wait => --Wenn im Wartezustand (tür zu, licht noch an) IF sechsSekFlag = '1'THEN folge_zustand <= state_idle; sechsSekFlag <= '0';--hier [/vhdl] denn,sechsSekFlag ist '1' für die dauer

FPGA, VHDL & Co. ·Stephen Trowbridge ·18.03.2012 08:39 ·12 Antworten

process immer laufen in VHDL

<= "000100" & "00" & "00111111"; when 3 => lut_data <= "001001" & "00" & "00100000"; when 4 => lut_data <= "010000" & "00" & "00111111"; when 5 => lut_data <= "010001" & "00" & "00111111"; when 6 => lut_data <= "010010" & "00" & "00101111"; when 7 => lut_data <= "010011" & "00" & "00101111"; when others =>lut_data <= "0000000000000000

FPGA, VHDL & Co. ·Plau Sein ·30.11.2007 22:28 ·13 Antworten

UART-Transmitter-Reset

-- sensitive to clock, asynch reset by reset -- -- storage data in internal register when data_ready = 1 -- ----------------------------------------------------------- data_storage : process (clk, reset, sent) is begin if reset = '1' or sent then data_register <= (others => '0');

<= 0; sent <= true; tx_ready_int <= '1'; when others => count_bit <= count_bit + 1; tx <= data_register(count_bit - 1); end case; end if; end if; end process data_send; end architecture behavior;

FPGA, VHDL & Co. ·Anfänger ·01.03.2007 09:00 ·1 Antworten

Quickstart CPLD

anstatt "count_out <= count_int" folgendes: with count_int select count_out <= "0001" when "00", "0010" when "01", "0100" when "10", "1000" when others; Da siehst Du ja dann ob die LEDs in der richtigen Reihenfolge leuchten.

-------------------------------------------------- The OFFSET constraint applies only to CPLDs when the clock is on a global clock net. This can be achieved by performing one of the following: 1. Placing the following constraint on the clock net NET myclock BUFG=CLK; (replace myclock with

FPGA, VHDL & Co. ·Michael ·19.05.2005 10:08 ·20 Antworten

CRC Berechnung für Ethernet

> OutByte <= CRCResultInverted( 15 downto 8); SendBufferState <= SendCRC1; when SendCRC1 => OutByte <= CRCResultInverted( 23 downto 16); SendBufferState <= SendCRC2; when SendCRC2 => OutByte <= CRCResultInverted( 31 downto 24); SendBufferState <= SendCRC3; when SendCRC3 => OutByte <= (others => '0'); TXOut <= '0'; SendBufferState <= Idle; [/vhdl] Es gibt noch den Hinweis, dass die ersten 32 Bit der MAC-Adresse invertiert

FPGA, VHDL & Co. ·Rooney Bob ·11.12.2018 12:08 ·11 Antworten

Fragen zum VHDL Drehgeber Code

<= '0'; ce <= '0'; error <= '1'; when "0100" => up_down <= '0'; ce <= '1'; error <= '0'; when "0101" => up_down <= '0'; ce <= '0'; error <= '0'; when "0110" => up_down <= '0'; ce <= '0'; error <= '1'; when "0111" => up_down

<= '0'; ce <= '0'; error <= '0'; when others => null; end case; end process; [/vhdl] up_down ist im Fehlerfall, bei keiner Bewegung und bei einer Rückwärtsbewegung '0'. Bei der Vorwärtsbewegung ist up_down '1'. ce ist bei keiner

FPGA, VHDL & Co. ·Reinhard J. ·25.11.2013 11:22 ·6 Antworten

Als Ingenieur in die Politik gehen

"other-oriented" feelings of sympathy and concern for unfortunate others > Personal Distress – measures "self-oriented" feelings of personal anxiety and unease in tense interpersonal settings Mit Fragen wie: "I daydream and fantasize, with some regularity, about

intelligence is important, but the unbridled enthusiasm has obscured a dark side. New evidence shows that when people hone their emotional skills, they become better at manipulating others. When you’re good at controlling your own emotions, you can disguise your true feelings. When you know what others are feeling

Ausbildung, Studium & Beruf ·hansi ·13.03.2018 16:06 ·138 Antworten

latch ?

<= s4; when s4 => next_state <= s1; end case; end process process2; process3 : process (state) begin case state is when s1 => outp <= '1'; when s2 => outp <= '1';

VHDL] signal DATA : std_logic_vector(15 downto 0) ; . . process(DATA,ACK, ... ) . DATA <= (others => '0'); . case xx is . . when DATA_H => ADDR <= "0"; if ACK = '1' then DATA(15 downto 8) <= DATA_IN; end if; when DATA_L => ADDR <

FPGA, VHDL & Co. ·chris ·06.07.2006 13:05 ·7 Antworten

VHDL - 'Warnung' vom Synthesetool (Synplify) unverständlich

: CL275 :"D:\test\test2\hdl\Test.vhd":42:11:42:11|Possible don't care specified as next state in others or default clause, or failure to extract state machine @END Der VHDL-Code dazu: [vhdl] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- library proasic3; entity Testprojekt

after 2 ns; else z <= z + 1 after 2 ns; end if; case z is when 1 => out_vec <= b"0001"; when 2 => out_vec <= b"0010"; when OTHERS => out_vec <= b"1001"; end case; -- if (z = 1) then -- out_vec

FPGA, VHDL & Co. ·Andreas Ramert ·17.09.2015 08:47 ·14 Antworten

Lauflicht mit CPLD

(clk) then cnt <= cnt+1; end if; end process; process(cnt) begin case cnt is when "000" => led <="00000001"; when "000" => led <="00000010"; when "000" => led <="00000100"; when "000" => led <="00001000"; when "000" => led <="00010000"; when "000" => led <="00100000"; when "000" => led <="01000000"; when "000" => led <="10000000"; when others => null; end case; end process; [/vhdl] MFG Falk

FPGA, VHDL & Co. ·D. E. ·21.02.2008 13:49 ·9 Antworten

nach Kündigung Auszeit & Selbststudium J2EE?

http://programmers.stackexchange.com/questions/25564/when-should-you-call-yourself-a-senior-developer You can call yourself a Senior when: - You can handle the entire software development life cycle, end to end - You lead others, or others look

person will leverage asynchronous programming, queuing, caching, logging, security and persistence when appropriate. When asked they can give a detail explanation of their choice and the pros and cons. In most cases they have mastered object oriented programming and design, this not an absolute other

Ausbildung, Studium & Beruf ·Roland Kr. ·03.05.2016 19:38 ·44 Antworten

VHDL Signal Teilen und in die nächst höhere Adresse schreiben

Adresse. Ich bekomme folgende Fehlermeldung: The data cannot be written to the memory correctly when only en_write is enabled, or the content of memory cannot be read. Kann mir jemand sagen, wo mein Problem liegt? Mein RAM [vhdl]library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all

downto 0); type ram_type is array (1023 downto 0) of logic_vector; signal ram : ram_type := ((others=> (others=>'0'))); begin process(Clk) begin if(en_read = '1') then outputsignal <= ram(to_integer(unsigned(addr2))); elsif(en_write = '1') then input_1 <= input(17 downto 0); input

FPGA, VHDL & Co. ·Markus G. ·06.12.2020 18:56 ·12 Antworten

Verhalten Sim vs Post Fit Sim

when "0011" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '1'; when "0100" => UP_DOWN <= '0'; C_ENABLE <= '1'; ERR <= '0'; when "0101" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0';

when "1111" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0'; when others => null; end case; end if; end if; end process QDecoder; end VERH;[/vhdl] nicht korrekt synthetisiert

FPGA, VHDL & Co. ·AlexW ·11.10.2007 09:53 ·5 Antworten

FSM Automat(für bestimmte zeit in einem zustand bleiben)

bar aber ich will da bleiben counter<=(others=>'0');--für bestimmte zeit Folge_z<=S4; end if; . . . MFG

counter <= (others => '0'); --für bestimmte zeit Folge_z <= S4; end if; [/vhdl] Was sagen den Folge_z und counter in der Simulation? Rick

FPGA, VHDL & Co. ·VHDL_Bginner ·12.06.2008 16:34 ·4 Antworten

2x werden die Daten 128-254 ausgegeben vom SRAM statt 0-254, woran liegt das bitte ?

txd => txd, tx_start => tx_start, tx_data => tx_data ); sram_io <= data_write when read_write='0' else (others=>'Z'); data_read <= sram_io; ub <= '0'; lb <= '0'; process (clk) begin if rising_edge (clk) then if (zustand = "001") then sram_adr <= sr_adr

rx_data; zustand <= "001"; end if; if sw(0) = '1' then sram_io <= (others => 'Z'); sram_adr <= (others => '0'); we <= '1'; ce <= '1'; oe <= '1'; end if; if sw(1) = '1' then sr_adr <= (others => '0');

FPGA, VHDL & Co. ·peter ·04.01.2015 16:31 ·4 Antworten

2 ATMega8 über SPI kommunizieren lassen

Mhz */ #endif #include <util/delay.h> void SPI_SlaveInit(void) { /* Set MISO output, all others input */ DDRB = (1<<PB4)|(1<<PB0); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void) { /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register

be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another Master selecting the SPI as a Slave and starting to send data to it.

Mikrocontroller und Digitale Elektronik ·Erich ·28.09.2008 18:08 ·18 Antworten

Synchroner Reset in Kombinatorik

(shift, reset, load, data, enable) begin if reset ='1' then shift_next <= (others => '0'); elsif load = '1' then shift_next <= data; elsif enable = '1' then shift_next <= std_logic_vector(SHIFT_LEFT(unsigned(shift), 1)); else shift_next

mit Kombinatorik gelöst ist. (nicht zu hause nachmachen, dies ist KEIN Reset): [vhdl] s_out <= (others => '0') when reset = '1' else shift(3); [/vhdl]

FPGA, VHDL & Co. ·EinVolvic ·26.11.2019 21:40 ·7 Antworten

Wie designe ich dieses case am besten?

habe eine verzweigte if-case-Anweisung in dieser Form: [vhdl] if RW = '0' then case DP_M is when "0000" => blabla when "0001" => blabla, etc end case; else case DP_M is when "0000" => blabla when "0001" => blabla, etc end case; [/vhdl] Ich habe also in beiden Fällen (also

Compiler mitteilen kannst, daß bestimmte Kombinationen nicht relevant sind, z.B. case Adr is when "00" => Data <= "0000"; when "01" => Data <= "0100"; when others => Data <= "----"; -- don't care end case; Grüße Klaus

FPGA, VHDL & Co. ·Christian Peters ·01.03.2007 12:59 ·7 Antworten

LCD von TerAsic mit Cyclone II von Altera

lut_data <= "001001" & "00" & "00100000"; when 4=> lut_data <= "010000" & "00" & "00111111"; when 5=> lut_data <= "010001" & "00" & "00111111"; when 6=> lut_data <= "010010" & "00" & "00101111"; when 7=> lut_data <= "010011" & "00" & "00101111"; when others=> lut_data <= "000000" & "00" & "00000000"; end case; im controller.vhd werden die bits von vorne abgeselen: if (mst < 17) then mst <= mst+1; end if; if (mst < 16) then

FPGA, VHDL & Co. ·Plau Sein ·22.02.2008 19:35 ·8 Antworten

Externens Ram statt FPGA RAM

we => ram_we ); end generate; Meine nicht funktionierende Lösung: ram_io <= RWD when ram_wr = '0' else (others => 'Z'); ram_a(12 downto 0) <= RAB; ram_a(19 downto 13) <="0000000"; ram_ce<='0'; ram_oe<='0'; ram_we <= ram_wr;

dem externen SRAM nachbilden können. > Meine nicht funktionierende Lösung: > ram_io <= RWD when ram_wr = '0' else (others => 'Z'); > ram_a(12 downto 0) <= RAB; > ram_a(19 downto 13) <="0000000"; > ram_ce<='0'; > ram_oe<='0'; > ram_we <= ram_wr; Das ist der Ansatz, es fehlt aber ncoh ne

FPGA, VHDL & Co. ·Dirk ·28.01.2007 18:34 ·36 Antworten

DCM und Ram Simulieren

'0'; signal reset_b : std_logic := '0'; signal dina : std_logic_vector(24 downto 0):= (others => '0'); signal addra : std_logic_vector(9 downto 0) := (others => '0'); signal wea : std_logic_vector(0 downto 0) := (others => '0'); begin -- dut -- component instantiation

BLK_MEM_GEN_V3_3.vhd DEBUG auf 1 setzen und mit Modelsim neu compilieren (memory_i <= memory when DEBUG=1;)

FPGA, VHDL & Co. ·Fresh ·19.01.2010 13:27 ·28 Antworten

Post-Map simulation mit ModelSim

overloaded matching definition for "+" Die zeilen 488..492 -- vsptr_out:SLV((adrbit-1) DOWNTO 0):=(OTHERS => '0'); IF (vsptr_inp = maxbuf) THEN -- Bufferpointer inkrem. vsptr_inp := (OTHERS => '0'); ELSE vsptr_inp := vsptr_inp + '1';--zeile 491 END IF; ist mir völlig unklar wo das fehler sein

-- vsptr_inp:SLV((adrbit-1) DOWNTO 0):=(OTHERS => '0'); für inp ist die gleiche Definition Gruss Anton

FPGA, VHDL & Co. ·Anton K. ·18.09.2024 08:57 ·148 Antworten

Xilinx Latch Problem

; when others => null; end case; end process p_memless; p_memzing : process (CLKxCI, RSTxRBI) begin -- process p_memzing if RSTxRBI = '0' then

heutzutage breite Bildschirme haben, bietet sich 'concurrent' geradezu an: [vhdl] InputDstRdyxS <= '1' when STATExDP = waitforSrc else '0'; [/vhdl] [vhdl] STATExDN <= waitforSrc when STATExDP = reset else count when STATExDP = waitforSrc and InputSrcRdyxS = '1' else

FPGA, VHDL & Co. ·finalcu ·14.11.2012 11:56 ·8 Antworten

Instruktion SLLI (Shift logical left i times)

" => m := 64; when "0111" => m := 128; when "1000" => m := 256; when "1001" => m := 512; when "1010" => m := 1024; when "1011" => m := 2048; when "1100" => m := 4096; when "1101" => m := 8192; when "1110" => m := 16384; when others => m := 32768; end case; y <= std_logic_vector(unsigned(a) * m); end process; [/vhdl] Number of Slices

FPGA, VHDL & Co. ·Unnormaley ·11.07.2012 07:45 ·4 Antworten

Bereich abprüfen

[vhdl] process (clk) begin if rising_edge(clk) then case pixel is when 0 => X <= "0001"; when 80 => X <= "0010"; when 160 => X <= "0011"; when 240 => X <= "0100"; when 320 => X <= "0101"; when 400 => X <= "0110"; when 480 => X <= "0111"; when others => X <= X; -- sonst Wert halten end case; end if; end process; [/vhdl]

FPGA, VHDL & Co. ·Miriam ·11.12.2008 13:22 ·4 Antworten