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Altera Timequest signal als clock identifiziert
if v_counter=0 then v_counter := CLK_MUL-1; case l_mstate is when IDLE => null; l_mstate <= IDLE; --set the machine to start. when START => l_obit <= '0'; l_mstate <= SEND; v_bcnt
vcnt_stbbit := vcnt_stbbit-1; end if; when others => l_mstate <= IDLE; end case; else v_counter := v_counter - 1; end if; end if; end if; end process P1; PO: process(l_obit,l_ready)
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VHDL Case statement covers only 4 out of 81 cases.
4 Möglichkeiten und nicht 86! CASE instruction_register( 15 DOWNTO 14 ) is when "00" => linear_address <= DPP0(3 downto 0)&(instruction_register( 13 DOWNTO 0 )); when "01" => linear_address <= DPP1(3 downto 0)&(instruction_register( 13 DOWNTO 0 )); when "10" => linear_address
Man sollte immer auch ein "when others" hinzufügen, auch wenn es eigendlich überflüssig ist, dann passiert das nicht. Du musst bedenken, dass man bei den erweiteren Signaltypen nicht nur mit 0 und 1 arbeitet, sondern auch mit undefinierten
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clocks in lattice ecp2
Hallo, wenn ich die Zeile led_out(0) <= '1' when Kanal_1 < pwm0 else '0'; auskommentiere, komm ich laut Trace Report auf 264MHz... Hab dann nur mehr eine 24MHz Clock, clk_pwm wird in der portmap vom pwm module auf clk_100 verdrahtet
Hallo, habe das jetzt ausprobiert: led_temp <= '1' when Kanal_1 < pwm0 else '0'; process (clk_pwm) begin if rising_edge(clk_pwm) then led_register <= led_temp; end if; end process; led_out(0) <= led_register
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CPLD defekt?
trigger1 <= '1'; Mode <= "0111"; end if; when "0111" => -- WE on '1'; counter <= to_X01(counter + 1); Mode <= "0000"; when "1000" => --
counter + 1); OE <= '0' after 20 ns, '1' after 60 ns; when OTHERS => Mode <= Mode; end case; end if; end if; end process; clock_source : process(clk_1, clk_2, clk_src) begin if (clk_src = '1') then clk <= clk_1; else
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Idee für universeller Decoder VHDL Code?
architecture RTL of DECODE_Xto1 is begin process (SEL, SIG_IN) begin case SEL is when "000" => SIG_OUT <= SIG_IN(0); when "001" => SIG_OUT <= SIG_IN(1); when "010" => SIG_OUT <= SIG_IN(2); when "011" => SIG_OUT <= SIG_IN(3); when "100" => SIG_OUT <= SIG_IN(4); when "101" => SIG_OUT <= SIG_IN(5); when "110" => SIG_OUT <= SIG_IN(6); when "111" => SIG_OUT <= SIG_IN(7); -- For simulation only when others => SIG_OUT <= 'X';
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Transistortester AVR
can you add please on makefile an option to compensate the voltage drop of the protection diode when misure the battery voltage ?
Hi Karl, i've added an external 2,5V reference to pd4 and i see 5.04v when i push the test button. Is that a good value ?
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Probleme bei der Umstellung von Verilog nach VHDL
when "0010" => mmc_doreg <= mmc_mosi_reg(5); when "0011" => mmc_doreg <= mmc_mosi_reg(4);
when "0110" => mmc_doreg <= mmc_mosi_reg(1); when others => mmc_doreg <= mmc_mosi_reg(0);
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ALLPOWERS S2000 PRO Reparaturhilfe
when i use j flash lite, everything goes ok with no errors, but when i read the flash, it's the old one, not the one i have just flased into it :(
shows 100% battery, the car port is flashing, the power button does not work as a power button, but when you hold it, it turns on the bluetooth, the ac button works but when you turn it on it pull up error 303 e0303 and shuts off but there is 220v at the output and you can't turn it off.... after few hours
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Flipflop auf rising und falling edge triggern (XC9572XL)
failed" severity error; -- fullcycle 1: read reset vector from 0x000000 to 0x000007 (SP + PC) when OVL_LOCAL is 1: reads from flash wait until fullcycle'event; A <= (others => 'U'), x"00" after speriod * 1.5, (others => 'U') after speriod * 8.0; ALOW <= (others => 'U'), x"0
= '1', '0' after speriod * 2.5, '1' after speriod * 7.1; D <= (others => 'U'), x"00" after speriod * 6.5, (others => 'U') after speriod * 8.0; wait for speriod * 0.75; assert (nOVR='Z') report "nOVR failed" severity error; assert (nDTACK='Z') report
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VHDL/DCM für Spartan-3E
process(clk) begin if (clk'event and clk ='1') then case sw is when "0000" => led <= "00000000"; when "1111" => led <= "10000001"; when "0001" => led <= "11111111"; when "0010" => led <= "01010101"; when "0100" => led <= "11001100"; when "1000" => led <= "00110011"; when others => end case; end if; end process output_ports; end Behavioral;
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Frage zur DDFS von Lothar Miller
Data_sin2 <= Result_sin2; when "00" => Result_sin2 <= Sinus_Rom ( to_integer(Address)); Data_sin2 <= std_logic_vector (-signed(Result_sin2)); when "01" => Result_sin2 <= Sinus_Rom (63-to_integer(Address)); Data_sin2 <= std_logic_vector (-signed(Result_sin2)); when others => null; end case; [/vhdl] das gleiche ist. Die Simulationsergebnisse haben aber einen kleinen Unterschied. Bei der case-Variante bekomme ich, sobald die Adresse 1 wird, immer komische
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KiCAD - Bibliotheken zusammenführen - wie geht das ?
Die beiläufige Erwähnung des "library cache" im KiCad Getting-Started ist auch nicht erhellend: "When you share a project, you should at least keep the library cache (-cache.lib) with it, to ensure that others can see your symbols" Lässt sich das Anlegen eines Library-Caches verhindern - will man
beiläufige Erwähnung des "library cache" im KiCad Getting-Started > ist auch nicht erhellend: "When you share a project, you should at least > keep the library cache (-cache.lib) with it, to ensure that others can > see your symbols" Ist weiter oben in diesem Post erklärt. ;O) > > Lässt
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Hamming Coder
könnte es also ganz ohne jeglichen Prozess so schreiben: [vhdl] with A select K <= "0111" when "00000", "0011" when "00001", "1001" when "00011", : : "1111" when "11101", "1001" when "11110", "1101" when others; -- "11111" [/vhdl] Und wenn
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Source Files zu Hexcode wandeln geht nicht
Init: On during Init * Status LED Ready: Flashing when Idle * Status LED Gate Open: On when the Gate is Open * ******************************************************************************* * The Phone has to support the following Commands: *
Init_Chip (void) { // Port B: // Bit 4 = Input // Others = Output DDRB = 0xEF; // DDR Port B: 1110 1111 PORTB = 0; // Init LED ON // Port D: // Bit 0 = Input // Others = Output DDRD = 0xFF;
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Xilinx Spartan 3AN -- DDR2 SDRAM Ansteuerung
auf Grundlage der UCF-Datei ist: [vhdl] SD_A : in std_logic_vector(15 downto 0) := (others => '0'); SD_BA : in std_logic_vector(2 downto 0) := (others => '0'); SD_RAS : in std_logic := '0'; SD_CAS : in std_logic := '0'; SD_CK_N : in std_logic := '0'; SD_CK_P :
<= counter - 1; end if; when RECEIVE => command_register <= "000"; if init_done = '1' then --and falling_edge(clk_i) then command_register <= "100"; input_adress <= "0000000000000000000000000
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Hilfe bei VHDL für Schieberegister mit einigen Extras
if; if (rising_edge(SS)) then if (slave_nr = SLV_NR) then case chan_nr is when "000" => gain_1_s <= gain; when "001" => gain_2_s <= gain; when "010" => gain_3_s <= gain; when "011" => gain_4_s <= gain; when "100" => gain_5_s <= gain; when "101" => gain_6_s <= gain; when "110" => gain_7_s <= gain; when "111" => gain_8_s <= gain; --when others => gain_1_s <= "000"; end case; end if;
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Ratschlag / Verbesserung zu vhdl-Progrämmchen
D_int select --Schiebestand an die Segmente DISP <= "1111001" when "00000001", "0100100" when "00000010", "0110000" when "00000100", "0011001" when "00001000", "0010010" when "00010000", "0000011" when "00100000", "1111000" when "01000000", "0000000" when "10000000", "1111111" when others; end Behavioral; [/vhdl]
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3 Achsen MEMS Beschleunigungs Sensorkit
dort im Datenblatt steht. Ab Seite 20 im Datenblatt ist doch alles beschrieben : bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address
(MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is 1 the address used to read/write data is incremented at every block.
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AEG induktionskochfeld HK654258 XB Relais Klickt, lüfter läuft und schaltet sich ab
electric problem. I search the internet many times with no success. I was even more motivated when the second half of the induction died. I googled my problem once more and found this post. I was so glad when I get to the electronic board and saw I had the problem you described. A few minutes
everyone to find. Could you please post the type, name and number of your Electrolux stove to help others find the solution?
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Flipflop und Latch
Anfängerfehler? Das ist eher die Regel: Kombinatorik im Prozess, keine Defaultzuweisung (else... bzw. when others...) --> Latch Eine unvollständige Sensitivity-Liste dazu, und das Ganze verhält sich in der Simulation grundlegend anders als in der Realität.
bitte jemand in VHDL übersetzen... [vhdl] : process (switch,a,b) begin case switch is when '1' => out1 <= a; when '0' => out2 <= b; end case; end process : [/vhdl] Hier ist sowohl out1 wie auch out2 nicht vollständig definiert, tauchen also nicht in jedem when-Pfad auf --> 2
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Custom Type Zuweisung per Namen und Wert
Aber bekomme ich mit der folgenden Beschreibung nicht noch einen: [vhdl] case count is when 0 => data_sel <= D0; when 1 => data_sel <= D1; when 2 => data_sel <= D2; when 3 => data_sel <= D3; when 4 => data_sel <= D4; when others => data_sel <= D0; end case;
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VHDL Maxplus2 Library Compile Error
wenigen Zeilen: [vhdl] signal reg : std_logic_vector (7 downto 0) := x"00"; : : reg <= inp when rising_edge(clk); outp <= x"00" when OE = 0 else reg; [/vhdl]
to_integer(unsigned(A))) <= D; end if; Q(to_integer(unsigned(A))) <= D; else BITS <= (others => '0'); Q <= (others => '0'); if LE_n = '0' then Q(to_integer(unsigned(A))) <= D; end if; end if; end process; end;[/vhdl] Edit: Aber ja, weil es im FPGA keine Latches
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Gray Code to 7-Segment
process (gray) begin case gray is -- abcdefg abcdefg when "00000" => zehner <= "1111110"; einer <= "1111110"; -- 00 when "00001" => zehner <= "1111110"; einer <= "0110000"; -- 01 when "00011" => zehner <= "1111110"; einer <= "1101101"; -- 02 : when "10001" => zehner <= "0110000"; einer <= "0110000"; -- 62 when others => zehner <= "0011111"; einer <= "1111001"; -- 63 end process; [/vhdl] > um es vielleicht in ein CPLD XC9572
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Timing FT2232H
then TXEFF<=TXE; end if; end process; if rising_edge(DCLK)then case(SSnd) is when WaitingForSendFlag => If AquisitionDone='1' then SSnd<=WaitForInitialTXELow; FinalAddress<=unsigned(WAddress); Counter<=unsigned(WAddress)+1; end if; when
SSnd<=Done; else SSnd<=Send1; end if; end if; when WaitForResume => if TXEFF='0' then SSnd<=ResumeState; end if; when Done=> WR<='1'; when others => SSnd <=WaitingForSendFlag; end case; end if; [/vhdl
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VHDL Prozess nur "anstupsen"
-- irgendwas resetten falls notwendig state:=0; else case state is when 0 => if trigger='1' then state:=1; end if; when 1 => -- einmalig irgendwas machen state:= 2; when 2 => -- bleibt für immer in 2 when others => state:=0; end case; end if; end if; end if; [/vhdl] oder sowas: [vhdl] -- läuft einmal, bleibt dann stehen process(clk) variable flag : std_logic := '0';
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Zugriff auf gleiches Signal aus verschiedenen Prozessen?
zwei einfache Schreibweisen: [vhdl] Foo : process(Selector) begin case Selector is when 1 => Address <= x"0123"; when 2 => Address <= x"4567"; when 3 => Address <= x"89AB"; when others => Address <= "ZZZZZZZZZZZZZZZZ"; end case; end process; [/vhdl] oder noch kürzer: [vhdl] Address <= x"0123" when Selector = 1 else x"4567" when Selector = 2 else x"89AB" when Selector = 3 else "ZZZZZZZZZZZZZZZZ"; [/vhdl]
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Anzeigefehler in ISE 10.1 oder habe ich etwas übersehen?
architecture MUX of CK_MUX is begin CMUX: process (CK_SEL, CK_IN) begin case CK_SEL is when "00" => CK_OUT <= CK_IN(0); when "01" => CK_OUT <= CK_IN(1); when "10" => CK_OUT <= CK_IN(2); when others => CK_OUT <= CK_IN(3); end case; end process CMUX; end architecture
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CPLD-Problem: moving average
SIG_OUT_DATA <= SIG_ADC1_DATA; end if; WHEN "0100" => --REFRESH MEAN --xxxx SIG_OUT_DATA <= SIG_ADC_MEAN; WHEN OTHERS => SIG_OUT_DATA <= SIG_OUT_DATA; END CASE;
Takt Latency eingeführt. Das ginge aber auch so: [vhdl] akku <= akku - akku/32 + in_data when rising_edge(clk); out_data <= akku/32 when rising_edge(clk); [/vhdl] Oder konservativer so: [vhdl] process begin wait until rising_edge(clk); akku <= akku
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Verständnisprobleme synchron, asynchron
definiert hast, speziell bei onehot-Codierung (such mal danach). Deshalb sollte man ein case-Zweig "when others => new_state <= irgendein_state; -- z.B. fehlerstate" vorsehen.
definiert hast, speziell bei onehot-Codierung (such mal danach). Deshalb sollte man ein case-Zweig "when others => new_state <= irgendein_state; -- z.B. fehlerstate" vorsehen. -> Ja, hilft aber z.B. auch nix, wenn man durch ein asynchrones Signal in einen gültigen State (der aber trotzdem falsch ist
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Glixon to Bcd wandler
architecture Behavioral of Glixon2BCD is begin process (glixon) begin case glixon is when "0000" => bcd <= "0000"; when "0001" => bcd <= "0001"; when "0011" => bcd <= "0010"; when "0010" => bcd <= "0011"; when "0110" => bcd <= "0100"; when "0111" => bcd <= "0101"; when "0101" => bcd <= "0110"; when "0100" => bcd <= "0111"; when "1100" => bcd <= "1000"; when "1000" => bcd <= "1001"; when others => bcd <= "0000"; end case; end process
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Vivado-Post-Synthesis Simulation liefert falsche Werte
process(CLK) begin if rising_edge(CLK)THEN case state_LED is When CNT1 => if SUM>2000000 then state_LED<=SETLEDS; else SUM <= SUM+1; end if; When SETLEDS => SUM<=0; LEDACTIVE<= not LEDACTIVE; state_LED<=CNT1; When others => state_LED<=CNT1; end case; end if; end process; LEDS<=LEDACTIVE; end Behavioral; [/vhdl]
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Statemachine hängt sich weg
3) Ich setzte den Debugvector meist ausserhalb der state machiene. Also: debugvector = "00001" when state_sig = STATE1 else "00010" when state_sig = STATE2 else ..... "10000" when state_sig = STATE_LAST; Abtakten vor Ausgabe nicht vergessen: process(clk) Begin if rising_edge(clk) then if reset = '1' then debug_output_pins <= (others => '0'); else debug_output_pins <= debugvector; end if; end if; end process; Dann läuft der debugausgang zwar einen Takt nach, aber er belügt dich nicht. schau dir den vhdlcode
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Can't determine definition of operator ""and"" -- found 0 possible definitions
begin if state = "100" then if inc'event and inc = '0' then case op(2 downto 0) is when "001" => res := a + b; when "010" => res := a - b; when "100" => res := (aV(7 downto 0) and bV(7 downto 0)); when others => res :=0; end case; end if; end if; end process; end behavioral; Auch when "100" => res := aV and bV; geht nicht. Die noetigen Libs sind doch eigentlich eingebunden? Auch kompiliert der Code, wenn ich die "and"-Zeile auskommentiere und das Programm arbeitet auf der Hardware
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Schieberegister und Latch
falsch. Gemeint war aber wohl [vhdl] constant C_SREG_RSTVAL : std_logic_vector(15 downto 0) := (others => '1); [/vhdl]
signal ncssr : std_logic_vector(2 downto 0) := "000"; begin ncssr <= ncssr(1 downto 0) & ncs when rising_edge(clk); -- ncs auf Mastertakt einsynchronisieren sreg <= sreg(14 downto 0) & sin when rising_edge(sclk); -- mit lokalem sclk einschieben par_out <= sreg when ncssr(
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Fehler bei Case-Anweisung
... process(clk) begin if rising_edge(clk) then case data_in(wert1 downto wert1 -3) is when "0000" => data_out <= '1'; when "0010" => data_out <= '1'; when "1011" => data_out <= '0'; when others => data_out <= '0'; end case; [/pre] Dies ist nur ein Beispielcode, da der
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Probleme mit SPI Übertragung (ATMega88 x2)
== 0){}; sendByte(c); } void init_spiMaster( void ){ /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void spiMasterTransmit(char cData) { /*
DD_SS DDB2 #define SS PB2 void init_spiMaster( void ){ /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void spiMasterTransmit(char cData) { /*
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HELP Exponentialfunktion
begin states: process (clock) begin if(clock'EVENT and clock='1') then case state is when IDLE => if(start='1') then state<=INIT; else state<=IDLE; end if; when INIT => --... --i<=1; fak<=1; pot<=1; res<=1; state<=RUN; when RUN => if(i>26) then state<=FINISH; end if; when FINISH => -- Ausgabe von e^x state<=IDLE; when others => state<=IDLE;
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Reset und Lock des DCM Cores
if rising_edge(clock) then case state is -- Reset the DCM Core when init => reset <= '1'; state <= work; when work => reset <= '0'; -- DCM Core has locked if locked = '1' then
reset_shreg(reset_shreg'left); if async_reset_pin = '1' then reset_shreg <= (others => '1'); end if; end process; [/vhdl] Ralf schrieb im Beitrag #2531520: > und noch was: Kannst Du da evtl. noch ein paar Quellen mit angeben? Es gab da m.E. mal was von Peter Alfke
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2 Incrementalgeber koppeln
"0101" => result := 0; when "0110" => result := 0; when "0111" => result := offset; when "1000" => result := offset; when "1001" => result := 0; when "1010" => result := 0; when "1011" => result := -offset; when "1100" => result := 0; when "1101" => result := -offset; when "1110" => result := offset; when "1111" => result := 0; when others => result := 0; end case;
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zusätzliche Arbeit
richtig bei 50MHz Takt?). Also schreibe ich folgendes: ... case cur_state is ... when count => if ( i >= 100000 ) then -- i ist die Zählvariable cur_state <= pulse; i := 0; else i := i + 1; -- tick
Dima Schmitt schrieb im Beitrag #2521891: > case cur_state is > ... > when count => > if ( i >= 100000 ) then -- i ist die Zählvariable > cur_state <= pulse; > i := 0; > else > i := i + 1; Das ist vermutlich
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AD-Wandler mit VHDL verwenden
architecture Behavioral of ADC_Compare is Signal ADC_1_Value, ADC_2_Value : signed(11 downto 0) := (others => '0'); begin SampleValues : Process(CLK) Begin if rising_edge(CLK)then ADC_1_Value <= signed(ADC_1); ADC_2_Value <= signed(ADC_2); end if; End Process; Greater <= '1' when ADC_1_Value > ADC_2_Value else '0'; Equal <= '1' when ADC_1_Value = ADC_2_Value else '0'; Less <= '1' when ADC_1_Value < ADC_2_Value else '0'; end Behavioral; [/vhdl] Setzt voraus, dass
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CAN Module von opencores
if ena = '1' then if rsta = '1' then doa <= (others => '0'); else doa <= ram(to_integer(unsigned(addra))); end if; if wea = '1' then ram(to_integer(unsigned
if enb = '1' then if rstb = '1' then dob <= (others => '0'); else dob <= ram(to_integer(unsigned(addrb))); end if; if web = '1' then ram(to_integer(unsigned
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[VHDL] Signal wird nicht gesetzt!
end if; end process; process(state) begin case state is when start => mem_req <= '0'; when fetch0 => irq_adr_switch <= "00"; PC_MODE <= '1'; PC_ENABLE <= '1'; when fetch1 => PC_bakup <= '1'; interrupted <= '1'; when decode => interrupted <= '0'; when others => null; end case; end process; end verhalten; [/vhdl] Das Problem ist nun folgendes: Von außen wird ein Reset angestoßen
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Synchronger Reset-Generator
sync: process(clk) begin if rising_edge(clk) then case reset_state is when RESET_0 => reset <= '1'; reset_state <= RESET_1; when RESET_1 => reset <= '1'; reset_state <= IDLE; when IDLE => reset <= '0'; when others => end case; end if; end process; [/vhdl] Initialisiert ist das State register per Init-Kommando. Diesen registrierten Reset-Ausgang verbinde ich mit allen anderen asynchronen
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altera quartus II .vhd in .Hex
CASE count1 IS WHEN 0=>led1<="0000"; WHEN 1=>led1<="0001"; WHEN 2=>led1<="0011"; WHEN 3=>led1<="0111"; WHEN OTHERS=>led1<="1111"; END CASE; count1:=count1+1; end if;
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Beschreibung einer State Machine
if (Reset = '1') then state := 0; else case state is when 0 => x <= '0'; state := 1; when 1 => x <= '1'; state := 0; when others => state := 0; end case; end if
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bit_Vektor VHDL
not phase; end if; end if; end process; serout <= bits(0); frame <= '1' when bitcnt/=0 else '0'; sclk <= phase; end Behavioral; [/vhdl] Hier die Stimuli der Testbench [vhdl] clk <= not clk after 50 ns; tb : PROCESS BEGIN wait for 270 ns; parin <= '1'&(548 downto 1=>'0')&'1'; parin <= (others=>'0'); parin(0) <= '1'; parin(5) <= '1'; parin(9) <= '1'; parin(15) <= '1'; load <= '1'; wait for 320 ns; load <= '0'; wait; -- will wait forever END PROCESS
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Aufruf einer CLK-gesteuerten FSM mittels einer Buttonflanke
out STD_LOGIC) is begin if (CLK_2Hz='1' and CLK_2Hz'event) then case State is when "000001" => State <= "000010"; LED1 <= '1'; when "000010" => State <= "000100"; LED1 <= '0'; when "000100" => State <= "001000"; LED1 <= '1'; when "001000" => State <= "010000"; LED1 <= '0'; when "010000" => State <= "100000"; LED1 <= '1'; when "100000" => LED1 <= '0'; when others => null; end case; end if; end Sequenz; ...... ...... ...... ...... ...... --UND
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Bit-Vektor Sortierproblem
Compiler -- Scheiss Tipparbeit process(ram_out, my_bit_vector) begin case ram_out is when "0000000" => sel_bit <= my_bit_vector(0); when "0000001" => sel_bit <= my_bit_vector(0); . . . when "1111111" => sel_bit <= my_bit_vector(127); when others => null; end process
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Wittig(welec) DSO W20xxA Hardware (Teil 2)
But when the problem is present, it's there from the start up of the device. When it's still cool...
our DSO. That can be: - temperture as first candidate for any (temporary) problem - vibrations when moving the device - mechanical forces when turning the range adjusters - mechanical forces when pushing any buttons Temperature as failure source is difficult to proove. Vibrations can be tested