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in VHDL 50MHz auf 2 Mhz runterteilen?
Lothar Miller schrieb im Beitrag #2133946: > when INIT => AUSGANG <= ALLEAN; > -- Achtung, jetzt kommt ein Zähler im kombinatorischen Teil einer 2-Prozess-FSM könnte ich diesen Zähler dann in dem getakteten Prozess, in dem
optimieren und weise die Lampensignale abhängig von den Zuständen direkt zu (z.B. mit einem CASE oder WHEN)...
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QUAD-SPI ARTY7 Developmentboard
begin if SWITCH_VEC(0) = '1' then -- RESET STATE_MACHINE <= (0 => '1', others => '0'); I_SPI_CLK <= '0'; I_SPI_CS <= '1'; I_SPI_DQ <= "ZZZZ"; else if rising_edge(PUSH_VEC(0)) then
variable VAR_I_SPI_DQ_NEXT : STD_LOGIC_VECTOR( 3 downto 0); begin VAR_I_SPI_DQ_NEXT := (others => 'Z'); for state in 0 to STATE_MACHINE'LEFT loop if STATE_MACHINE(state) = '1' then -- command (8 Takte) if state = 0 or state =
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Lothar Millers VectorToBCD Koverter mit großen Zahlen
signal stelle : unsigned(3 downto 0) := "1101"; signal wert : unsigned(47 downto 0) := (others => '0'); begin process variable x : unsigned(47 downto 0):= (others => '0'); begin wait until rising_edge(clk); busy <= '0'; case state is when idle => -- wert <= to_integer(unsigned(vector)); wert <= unsigned(vector); --Zeile28 if (start='1') then stelle <= "1101";
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RTC Kapazitäten abgleichen, Genauigkeit erhöhen (STM32)
Another situation that is common to overshoot problem is having an input to the RTC at 5V when the RTC is in battery-backup mode. This can be a problem in systems that systematically shut down certain circuits but keep others powered up. It is very important to ensure there are no input signals
RTC that are greater than the battery voltage (unless stated otherwise in the device data sheet) when the device is in battery-backup mode. 2. Wrong crystal. A RTC typically runs slow if a crystal with a specified CL is less than the CL of the RTC. The severity of the inaccuracy is dependent on
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ZPU: Opensource Softcore CPU Projekt für Xilinx Spartan-3 FPGA Board
during the process. How to deal with a timer module to send me the values of the mentioned quantities when the process runs on my ZPU? Can you suggest me some way to deal with the above problems? Grüße, Piyush
so much for your last reply. I am still working on the dual core implementation and will post here when I get some success or get stuck somewhere. :) On the other hand, I wanted to ask that do the others who have worked on the ZPU have faced this problem with the ZPU external RESET signal? If the
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Pseudozufallszahlengenerator und Signaturanalysator Probleme
coeff_AND : std_logic_vector (0 to NN-1); SIGNAL Q : std_logic_vector (0 to NN) := (others => '0'); SIGNAL ausgang_xor : std_logic_vector (0 to NN-1); SIGNAL BACK : std_logic := '1'; begin -- FIRST FF D_FF_FIRST: d_ff PORT MAP( D => ausgang_xor(0
<= coefficient_vector(NN-1) AND BACK; BACK <= (Q(NN) AND coefficient_vector(NN-1)) WHEN (func_select = '0') ELSE Q(NN); -- Ausgangssignal auf Ausgangsvektor geben. x(NN-1) <= Q(NN); end Behavioral; [/vhdl]
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Automower G3 mit USB Diagnoseport fernsteuern?
@Kim The mower responses only on commands when its mowing or charging. Just a remark, if you‘re trying to communicate with the mower in a disassembled condition.
test the serial connection, you need to assemble the mower and let it work? No serial connection when dissembled? Thanks, Pieter
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transistor in sättigung
Frustration-Aggression Theory: Frustration is a feeling of tension that occurs when our efforts to reach some goal are blocked. When this occurs, it can produce feelings of anger, which in turn can generate feelings of aggression and aggressive behavior. This theory has been
can't punch annoying co-workers), will redirect this frustration and act aggressively toward others.
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exakter Frequenzteiler
schreibst du das nicht so: IF rising_edge(takt) zaehler <= zaehler + 1; CASE zaehler IS WHEN 12000000 => ausgang <= '0'; zaehler <= 0; -- Zähler zurücksetzen WHEN OTHERS => ausgang <= '1'; END CASE END IF; Das Zählersignal muss dann aber
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Hex.file erstellen
Specify relative path to RobotArm library files here. CAT_LIB_PATH=../../RobotArmLib CAT_LIB_PATH_OTHERS= $(CAT_LIB_PATH)/RobotArmBase $(CAT_LIB_PATH)/RobotArmI2C # Object files directory # To put object files in current directory, use a dot (.), do NOT make # this an empty or blank macro
directory that has spaces, enclose it in quotes. EXTRAINCDIRS = $(CAT_LIB_PATH) $(CAT_LIB_PATH_OTHERS) # Compiler flag to set the C Standard level. # c89 = "ANSI" C # gnu89 = c89 plus GCC extensions # c99 = ISO C99 standard (not yet fully implemented) # gnu99 = c99 plus
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Vivado Simulation stoppt vor Ende der Simulationszeit
begin if (rising_edge(clk)) then case (current_state) is when waitForADC => filter_rdy_intern <= '0'; data_read_ready <= '0'; sop := (others => '0'); counter_filter := 0; when readData => x(0) <= "0" & x_in; --Neues Datum einlesen data_read_ready <= '1'; when filter => if (counter_filter
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wie groß muß das CPLD ungefähr sein ?
-- Reset bei logisch 0 am -- manuellem Clock Eingang sample <= (others => '0'); end if; [/vhdl] Denn die meiste Zeit ist hier die else erfüllt. Das Schieberegister sample wird also immer zurückgesetzt. Und weil es dann wieder ungleich "110" ist, wird es beim
auch nochmal ansehen: [vhdl] -- Takt ungeteilt when "11" => divider <= 0; countUP <= '1'; [/vhdl] In diesem Fall ist countUP immer '1', das bringt dich dann dort in Schwierigkeiten: [vhdl] if countUP = '1' then
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Federkontakte im 1 mm Raster
regarding this and other pages and types of info really show it. I'm usually not on the web very much but when I am bored im usually avidly hunting for this sort of knowledge or others similarly related to it. When someone gets a chance, check out at my site: [url=https://jonsipes.com/practice-areas/representing-minors-in-disability-hearings
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Diode an Reset
cathode to +5vdc. The prior auto-reset wiring design could cause an intermittent latch-up problem when auto-reset was activated. This 'latch-up' problem could effect most prior arduino boards, not just the Uno boards, but was a little more prevalent when the Uno R2 design added a pull-down resistor
as frequently. There was a long post on this forum about this problem and I spend some time with others helping to try and verify if it was a real problem or not. It was real but pretty difficult to demonstrate in a repeatable manner. The problem was that the capacitance coupled reset pulse was sometimes
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Additions Funktion mit VHDL
process(func,cin,operand_1,operand_2) begin case Func is when "00001" => -- Addition Add(Operand_1,Operand_2,res); .... when others => null; -- leere Anweisung end case;
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Mit std_logic_vector Mittelwert berechnen
Ich habe die Idee mit unsigned nun umgesetzt, schauen wir mal, ob es auf Anhieb klappt. [vhdl] when stay => if valid = '1' then summe_u <= summe_u + unsigned(data); count_wr <= count_wr + 1; if count_wr = 1023 then cam_state <= next; else cam_state3 <= stay; end if; end if; when next => wr_en_fifo <= '1'; din_fifo <= std_logic_vector(summe_u(25 downto 10)); cam_state <= stay; summe_u <= (others => '0'); [/vhdl] Vielen Dank ür die Hinweise und Hilfe!
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Fehler beim Auslesen aus Dual Port RAM
when READ_POSSIBLE => if (sig_data_in_fifo = '1') then rs232_fifo_addr_en_s <= '1'; rs232_fifo_addr_s <= std_logic_vector(to_unsigned(data_in_fifo_cnt,7)); state_rxd
<= CHECK_STATE; end if; when CHECK_STATE => if (rs232_fifo_addr_s <= rs232_data_cnt_s) then data_in_fifo_cnt <= data_in_fifo_cnt + 1; else data_in_fifo_cnt <= 0; end if;
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Custom IP-Core für Mittelwert/Standardabweichung
folgendes: [vhdl] if Bus2IP_Clk'event and Bus2IP_Clk = '1' then case slv_reg_write_sel is when "01" => .... when others => null; end case; end if; [/vhdl] 2. Wie kann ich Mittelwert/Standardabweichung mit einer variablen Anzahl von Elementen berechnen lassen? Reicht
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Xilinx IOs als open-collector
Beispiele VHDL(nur für die Output-Seite): Datenbus bidirektional, push-pull: my_databus <= data when rd_n = '0' else (others=>'Z'); I2C, Open-Drain am SDA: sda <= '0' when sda_intern = '0' else 'Z'; -- keine '1' !
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toolchain für STM8 unter Windows
the Makefile working for Windows. If you get it, I would love have it and put on the project so others can take advantage of it.
> I don't know how to put the Makefile working for Windows. When "sdcc.exe" is in your %PATH% simply change #Compiler CC = /home/cas/software/stm8-binutils/bin/sdcc to #Compiler CC = sdcc.exe This works for the MinGW-Version of sdcc and make. I do
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Regelkreis für Modellbauservo
be * helpful if we want the controller to be aggressive at some * times, and conservative at others. in the example below * we set the controller to use Conservative Tuning Parameters * when we're near setpoint and more aggressive Tuning * Parameters when we're farther away. ***********
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VHDL Daten aus Datei
read(lin, space); hread(lin, data); CASE cmd IS WHEN "wr" => RW_fh <= '1'; IO_Data_fh_write <= data; WHEN "rd" => RW_fh <= '0'; WHEN OTHERS => NULL; END CASE
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FPGA Vhdl Lauflicht (variable Geschwindigkeit)
process clock; -- prescaler selector process (control) begin case control is when "00" => div <= 5; when "01" => div <= 10; when "10" => div <= 50; when "11" => div <= 100; when others => null; end case; end process; -- variable prescaler
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The Siemens S65 132x176, 65536 color display with AVR
Datenblatt Seite 7 RS: "When using SPI, fix it to Vcc or GND level"
data sending) by making an 1s delay between each line change, and figured out, that the lines appear when the CLOCK line is low. When it goes high, the picture gets back to normal.
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ZYBO Zynq-7000 Development Board - erste Schritte
tastgradnext : integer := 0; signal button : std_logic; begin tastgradnext <= tastgrad +10 when btn_0 else tastgrad-10; button <= (btn_0 xor btn_1); tastgrad <= tastgradnext when rising_edge(button); process begin wait until rising_edge(Clk_48kHz); counter1 <= counter1 + 1; pwm <= '1' when 0 <= counter1 and counter1 < tastgrad else '0'; if counter1 = 10d"960" then counter1 <= 10d"0"; end if; end process; end Archi;[/vhdl]
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erstes CPLD/FPGA Projekt ...
Versuche es mal so : D <= D_LS when CS = '0' and RW = '1' else (others => 'Z'); D_LS <= D when CS = '0' and RW = '0' else (others => 'Z'); RW_LS <= RW; ... Das ganze außerhalb eines Prozesses. Klaus
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Anfängerfrage Submodule einbinden
kuriose Aufgabe? Das ist in VHDL eigentlich ein Dreizeiler... [vhdl] yout <= a(6 downto 0) & '0' when lr_dir='1' else '0' & a(7 downto 1); [/vhdl]
entity work.shiftright(Behavioral) port map (a=> a , y=>yr); with lr_dir select yout<=yl when '0', yr when others; end Behavioral;[/vhdl] exemplarisch Submodul links: [vhdl]library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity shiftleft is generic( N
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Multiplikation mit einem std_logic möglich?
-- falls ergebnis ein Vektor ist ergebnis <= std_logic_vector(to_unsigned(3,ergebnis'length)) when datain(20)='1' else (others=>'0'); -- falls ergebnis ein Integer ist ergebnis <= 3 when datain(20)='1' else 0; [/vhdl]
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Bombardierung des Iraks durch die RAF - 1921!
with gas attacks by the army in the south, bombing by the fledgling RAF in both north and south. When Iraqi tribes stood up for themselves, we unleashed the flying dogs of war to "police" them. Terror bombing, night bombing, heavy bombers, delayed action bombs (particularly lethal against children)
God and no one is to be blamed." One RAF officer, Air Commodore Lionel Charlton, resigned in 1924 when he visited a hospital after such a raid and faced armless and legless civilian victims. Others held less generous views of those under their control. "Woe betide any native [working for the RAF] who
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STM32H743 mit 32MByte externem SDRAM
for this Board and display and lvgl is running fine on this board due to a lot of RAM. edit: when I remove the I2C read, the it works, also your logo is displayed on the screen.
forum and I don't know what I do wrong, I can't read the memory at all. I use stm32 cube ide, and when I tried to read memory address 0xC0000000, it shows '????????', not a random hex, even when I tried to write some data, nothing changed. This is my first time dealing with sdram so I follow all the
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Problem mit meinem Projekt (Quadrocopter)
*******************************/[/color] [color=#7E7E7E]/* this is the value for the ESCs when they are not armed[/color] [color=#7E7E7E] in some cases, this value must be lowered down to 900 for some specific ESCs, otherwise they failed to initiate */[/color] #define MINCOMMAND
]/* Temporarily Disables GPS_HOLD_MODE to be able to make it possible to adjust the Hold-position when moving the sticks.*/[/color] #define AP_MODE 40 [color=#7E7E7E]// Create a deadspan for GPS.[/color] [color=#7E7E7E]/************************ Assisted AcroTrainer ***********
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Spartan3 intern RAM mit 4096Byte ->2^12 mit 8 Bit breite
port map (WE=>WEINT, D=>Din(7 downto 0), CLK=>CLK, A=>A, O=>Dint(7 downto 0)); Dout <=Dint when EN='1' else (others=>'Z'); end Behavioral; ------------------------------------------------------------------ entity ram is Port ( WE : in std_logic; CLK : in std_logic;
std_logic_vector(63 downto 0); variable int: integer range 0 to 63; begin enable_var := (others=>'0'); INT := conv_integer(To_StdLogicVector(HADR)); enable_var(int):='1'; enable <=enable_var; end process P1; GEN: for I in 63 downto 0 generate RAM_BLOCK: RAM32
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Verständnisfrage SPI
Slave laufen! Anbei der Code: void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<CPOL)|(1<<CPHA)|(0<<SPR1)|(1<<SPR0); //1/8 FCPU SPSR = 1<<SPI2X
Hab glaub ich den Fehler gefunden. This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SSis configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will
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std_logic_vector zu signed
std_logic_vector(x downto 0) (x kann beliebig groß sein je nach anforderung) nach begin temp <= (others => '1'); value_long <= temp((value_long'high - value_short'high) - 1 downto 0)&value_short when (signed(value_short) < 0) else CONV_STD_LOGIC_VECTOR(0, LVEC
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ATMega328P - Hardware SPI - SCK hoert nach ein paar Durchlaeufen auf zu wackeln
sollte aufhoeren bei µCs Vermutungen anzustellen :) Ja, dagegen hilft das /Datenblatt/... [pre] When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin which does not affect
be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input ... the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. [/
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Blockram mit Statemaschine ansprechen
Beispiel. [vhdl] process(clk) begin if rising_edge(clk) then case state is when idle => if do_write = '1' then state <= write; adr <= adr_wr; data <= data_in; we <= '1'; elsif do_read='1' then adr <= adr_rd; end if; when write => we <= '0'; state <= idle; end case; end if; end process; [/vhdl] MFG Falk
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FPGA synthetisierung
rising_edge(clk)) then x := x+1; end if; if(uart_start = '1') then case x is when 0 => clk_out <= '0'; when 1 => clk_out <= '0'; when 2 => clk_out <= '1'; when 3 => clk_out <= '1'; when 4 => clk_out <= '0'; uart_ablauf := '1'; when OTHERS => clk_out
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Problem mit Wishbone Builder "and/or"
funktionieren? Ich habe jetzt einen Multiplexer wie folgt umgesetzt: [vhdl] readdata <= wbs1_dat_i when (wbs1_ss = '1') else wbs2_dat_i when (wbs2_ss = '1') else (others => '0'); [/vhdl] Damit funktioniert es natürlich. Viele Grüße, Michael
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MP3 Aktive Box mit NFC Leser und SD Karten Slot und 1200mAh Akku für 9,99
do with upper-case vs. lower-case - Windows doesn't distinguish between upper-case and lower-case when accessing FAT-formatted media, but these devices often do, and that can lead to confusing behaviour.
day. ---------------- We are studying a system that will revolutionize the activation of audios. When it is more advanced we will let everyone know.
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Probleme beim Einbinden einer Instanz
end if; end process; [/vhdl] Oder ganz ohne Prozess: [vhdl] FERTIG <= VERZÖGERUNG when rising_edge(CLK); [/vhdl] BTW: VERZÖGERUNG Ich würde Umlaute im VHDL-Code tunlichst meiden...
macht man nicht getaktet. Machs halt mal zu ner FSM so von wegen [vhdl] CASE (COUNTER) IS WHEN 0 => READ_DONE_S <= '1'; WHEN OTHERS => READ_DONE_S <= '0'; END CASE; auslesen_addrb_s <= auslesen_addrb_s + 1; [/vhdl] Ist nich ganz deins aber zum Testen sollts das tun
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Komischer Fehler: ERROR:HDLCompiler:463 - "../Huffman.vhd" Line 170
>if DECODExC'event then v.dec_len := LENGTHxC; end if; -- Shift only when new data available if NEXTxC'event then v.dec_shift := v.dec_shift(31 downto 0) & DATAxC; v.dec_ptr := v.dec_ptr + 32; end if; Weiter oben hatte ich für den
F. D. schrieb im Beitrag #2572215: > -- Shift only when new data available > if NEXTxC'event then > v.dec_shift := v.dec_shift(31 downto 0) & DATAxC; > v.dec_ptr := v.dec_ptr + 32; > end if; Da liegt der Hund begraben
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LCD Ansteuerung
display data RAM is set in the display start line register and displayed at the top of the screen. When the display duty cycle is 1/64 or others(1/32 - 1/64), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed. blick da mit meinem
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freies USB-Logo?
developers/tools/obsoletevids093009.pdf), wie z.B. MCS Electronics "That changed in June 2009 when USB-ORG wrote an email that it was not permitted to sell VID or PID. MCS pointed out that in The Netherlands you can not enforce or change rules AFTER a product/service is sold. So we continued as
noch sonst irgendwas ohne schriftliche Erlaubnis: > "They may not be sold, transferred, or used by others, directly or > indirectly, except in special circumstances and then only upon prior > writtenapproval by USB-IF. Unauthorized use ... are strictly > prohibited." Naja, außer man kann dem USB
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FT800 / FT810 Library
spending your time on my problem. SPDA is a data pin of the Serial communication bus. it must be GND when not use
While it is not really obvious for me when I look at the picture, measuring height and width shows a clear deviation, yes. When you already use BT815 for extended font support, why not use pictures for the circles? After all, these have
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Wittig- Oszi meldet sich nicht mehr
disassembled and reassembled these scopes? Michael, what's the status of your scope? From the time when the scope worked I remember that it emitted quite a lot of heat, but I don't know from which of the chips it came. I only know that chips can degrade when they become too hot. Another personal experience
replacement makes my scope work again I will post the component I used for the repair - that should help others with the same problem. Michael
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Pickit2 UART Frage
and Enable Receipt (CREN=1) BAUDCTL=0; } void putch(unsigned char data) { // Send Data when TXIF bit is ready while(!TXIF) continue; TXREG = data; } unsigned char getch(void) { // Get Data when RCIF bit is ready while(!RCIF) continue; return RCREG; } void main(void)
= 0x03; // Input for RA0 and RA1 TRISC = 0x07; // Set RC0,RC1 and RC2 as input others as Output ANSEL = 0x71; // Set PORT AN0, AN4, AN5 and AN6 as analog input ANSELH = 0x00; // Set PORT AN8 to AN11 as Digital I/O PORTC = 0x00; // Turn Off all PORTC /
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257 Werte 1 byte
dann so gemacht: [vhdl] oslv_byte <= std_logic_vector(u_tmp( (i_width-2) downto (i_width-9))) when u_tmp(i_width-1) = '0' else (others=>'1'); [/vhdl] Dadurch ist oben natürlich das ganze nichtlinear, was sich ja auch nicht vermeiden lässt es wird ja irgendwie auch der Wertebereich gestaucht.
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Weiterentwicklung der Hardwarebrschreibungssprachen
it really a problem? It seems to me that successful projects are often linked to one person, even when there are obviously a lot of others making significant contributions (like in the MyHDL project, thank you all!) Somehow it seems to give projects an identity.
continually have to clean up the mess behind them. http://stackoverflow.com/questions/6155675/when-should-i-use-std-logic-vector-and-when-should-i-use-other-data-types Jan
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Arduino Codeänderung ---> Anfänger braucht Hilfe !
adc_key_in < 555) return btnLEFT; if (adc_key_in < 790) return btnSELECT; return btnNONE; // when all others fail, return this...[/avrasm] Es wäre nett wenn mir jemand von den AVR Spezis dabei helfen könnte ;-) Gruß
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VHDL Coolrunner Delay line wird wegoptimiert trotz keep
attribute KEEP of chain : signal is "true"; begin chain <= chain (14 downto 0) & not(input) when reset='0' else (others=>'0'); process ( chain) begin taps <= chain(15); [/vhdl]