Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Datei

    SOURCE.vhd

    downto 0) ); end SOURCE; architecture Behavioral of SOURCE is signal COUNT : unsigned(9 downto 0):=(others => '0'); signal Schalter_grenze : unsigned(9 downto 0):=(others => '0'); begin Schalter_grenze <= unsigned(SCHALTER(9 downto 0)); -- Hier hab ich es umgewandelt --DATA_OUT <= DATA_IN; Hier hatte ich

    in „VHDL Code Aufgabe, HILFE! :/“ · FPGA, VHDL & Co. ·

  • Thread

    Probleme mit SPI Übertragung (ATMega88 x2)

    == 0){}; sendByte(c); } void init_spiMaster( void ){ /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void spiMasterTransmit(char cData) { /*

    DD_SS DDB2 #define SS PB2 void init_spiMaster( void ){ /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK)|(1<<DD_SS); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void spiMasterTransmit(char cData) { /*

    Mikrocontroller und Digitale Elektronik ·Frederik Krämer · ·13 Antworten

  • Thread

    HELP Exponentialfunktion

    begin states: process (clock) begin if(clock'EVENT and clock='1') then case state is when IDLE => if(start='1') then state<=INIT; else state<=IDLE; end if; when INIT => --... --i<=1; fak<=1; pot<=1; res<=1; state<=RUN; when RUN => if(i>26) then state<=FINISH; end if; when FINISH => -- Ausgabe von e^x state<=IDLE; when others => state<=IDLE;

    FPGA, VHDL & Co. ·Corina Thiel · ·5 Antworten

  • Thread

    Reset und Lock des DCM Cores

    if rising_edge(clock) then case state is -- Reset the DCM Core when init => reset <= '1'; state <= work; when work => reset <= '0'; -- DCM Core has locked if locked = '1' then

    reset_shreg(reset_shreg'left); if async_reset_pin = '1' then reset_shreg <= (others => '1'); end if; end process; [/vhdl] Ralf schrieb im Beitrag #2531520: > und noch was: Kannst Du da evtl. noch ein paar Quellen mit angeben? Es gab da m.E. mal was von Peter Alfke

    FPGA, VHDL & Co. ·Hans-Werner · ·16 Antworten

  • Thread

    2 Incrementalgeber koppeln

    "0101" => result := 0; when "0110" => result := 0; when "0111" => result := offset; when "1000" => result := offset; when "1001" => result := 0; when "1010" => result := 0; when "1011" => result := -offset; when "1100" => result := 0; when "1101" => result := -offset; when "1110" => result := offset; when "1111" => result := 0; when others => result := 0; end case;

    Mikrocontroller und Digitale Elektronik ·R. E. · ·58 Antworten

  • Thread

    zusätzliche Arbeit

    richtig bei 50MHz Takt?). Also schreibe ich folgendes: ... case cur_state is ... when count => if ( i >= 100000 ) then -- i ist die Zählvariable cur_state <= pulse; i := 0; else i := i + 1; -- tick

    Dima Schmitt schrieb im Beitrag #2521891: > case cur_state is > ... > when count => > if ( i >= 100000 ) then -- i ist die Zählvariable > cur_state <= pulse; > i := 0; > else > i := i + 1; Das ist vermutlich

    FPGA, VHDL & Co. ·Dima Schmitt · ·18 Antworten

  • PDF

    vhdlqrc.pdf

    sequential_statement}] italic VHDL-1993 end [procedure] ID]; 2.1. T YPE DECLARATIONS for LABELID | others | all : COMPID use 1. L IBRARY U NITS type ID is ( {ID,} ); (entity [LIBID.]ENTITYID [( ARCHID )]) | type ID is range number downto | to number; (configuration [LIBID.]CONFID) [{use_clause}] [[generic

    in „Signed / Std Logic“ · FPGA, VHDL & Co. ·

  • Thread

    AD-Wandler mit VHDL verwenden

    architecture Behavioral of ADC_Compare is Signal ADC_1_Value, ADC_2_Value : signed(11 downto 0) := (others => '0'); begin SampleValues : Process(CLK) Begin if rising_edge(CLK)then ADC_1_Value <= signed(ADC_1); ADC_2_Value <= signed(ADC_2); end if; End Process; Greater <= '1' when ADC_1_Value > ADC_2_Value else '0'; Equal <= '1' when ADC_1_Value = ADC_2_Value else '0'; Less <= '1' when ADC_1_Value < ADC_2_Value else '0'; end Behavioral; [/vhdl] Setzt voraus, dass

    FPGA, VHDL & Co. ·Eslon · ·52 Antworten

  • PDF

    MOC3052M-D.PDF

    except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98AON13450G Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: PDIP6 8.51x6.35, 2.54P PAGE

    in „Phasenanschnitt-Steuerung funktioniert nicht“ · Analoge Elektronik und Schaltungstechnik ·

  • PDF

    MOC3052M-D.PDF

    except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98AON13450G Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: PDIP6 8.51x6.35, 2.54P PAGE

    in „Leistung für Gatewiderstand Triac“ · Analoge Elektronik und Schaltungstechnik ·

  • Thread

    CAN Module von opencores

    if ena = '1' then if rsta = '1' then doa <= (others => '0'); else doa <= ram(to_integer(unsigned(addra))); end if; if wea = '1' then ram(to_integer(unsigned

    if enb = '1' then if rstb = '1' then dob <= (others => '0'); else dob <= ram(to_integer(unsigned(addrb))); end if; if web = '1' then ram(to_integer(unsigned

    FPGA, VHDL & Co. ·Heinrich H. · ·9 Antworten

  • Thread

    [VHDL] Signal wird nicht gesetzt!

    end if; end process; process(state) begin case state is when start => mem_req <= '0'; when fetch0 => irq_adr_switch <= "00"; PC_MODE <= '1'; PC_ENABLE <= '1'; when fetch1 => PC_bakup <= '1'; interrupted <= '1'; when decode => interrupted <= '0'; when others => null; end case; end process; end verhalten; [/vhdl] Das Problem ist nun folgendes: Von außen wird ein Reset angestoßen

    FPGA, VHDL & Co. ·Unnormaley · ·5 Antworten

  • Thread

    Synchronger Reset-Generator

    sync: process(clk) begin if rising_edge(clk) then case reset_state is when RESET_0 => reset <= '1'; reset_state <= RESET_1; when RESET_1 => reset <= '1'; reset_state <= IDLE; when IDLE => reset <= '0'; when others => end case; end if; end process; [/vhdl] Initialisiert ist das State register per Init-Kommando. Diesen registrierten Reset-Ausgang verbinde ich mit allen anderen asynchronen

    FPGA, VHDL & Co. ·Robert S. · ·6 Antworten

  • Thread

    altera quartus II .vhd in .Hex

    CASE count1 IS WHEN 0=>led1<="0000"; WHEN 1=>led1<="0001"; WHEN 2=>led1<="0011"; WHEN 3=>led1<="0111"; WHEN OTHERS=>led1<="1111"; END CASE; count1:=count1+1; end if;

    Mikrocontroller und Digitale Elektronik ·Bruce G. · ·3 Antworten

  • Datei

    LCD_CTRL.vhd

    incrementieren x"0C", -- Display ein, Unterstrich-Cursor, Cursor ein x"02", -- Cursor Home, Zeile oben others => x"01" -- Clear Display -- others => (std_logic_vector(to_unsigned(character'pos('X'),8))) ); attribute ram_style: string; attribute ram_style of ram : signal is "block"; signal index : integer range

    in „EA DOG-M initialisieren“ · FPGA, VHDL & Co. ·

  • Thread

    Beschreibung einer State Machine

    if (Reset = '1') then state := 0; else case state is when 0 => x <= '0'; state := 1; when 1 => x <= '1'; state := 0; when others => state := 0; end case; end if

    FPGA, VHDL & Co. ·VHDL-Anfänger · ·14 Antworten

  • Thread

    bit_Vektor VHDL

    not phase; end if; end if; end process; serout <= bits(0); frame <= '1' when bitcnt/=0 else '0'; sclk <= phase; end Behavioral; [/vhdl] Hier die Stimuli der Testbench [vhdl] clk <= not clk after 50 ns; tb : PROCESS BEGIN wait for 270 ns; parin <= '1'&(548 downto 1=>'0')&'1'; parin <= (others=>'0'); parin(0) <= '1'; parin(5) <= '1'; parin(9) <= '1'; parin(15) <= '1'; load <= '1'; wait for 320 ns; load <= '0'; wait; -- will wait forever END PROCESS

    FPGA, VHDL & Co. ·Martin · ·18 Antworten

  • Thread

    Aufruf einer CLK-gesteuerten FSM mittels einer Buttonflanke

    out STD_LOGIC) is begin if (CLK_2Hz='1' and CLK_2Hz'event) then case State is when "000001" => State <= "000010"; LED1 <= '1'; when "000010" => State <= "000100"; LED1 <= '0'; when "000100" => State <= "001000"; LED1 <= '1'; when "001000" => State <= "010000"; LED1 <= '0'; when "010000" => State <= "100000"; LED1 <= '1'; when "100000" => LED1 <= '0'; when others => null; end case; end if; end Sequenz; ...... ...... ...... ...... ...... --UND

    FPGA, VHDL & Co. ·Gilles Backhus · ·3 Antworten

  • Thread

    Bit-Vektor Sortierproblem

    Compiler -- Scheiss Tipparbeit process(ram_out, my_bit_vector) begin case ram_out is when "0000000" => sel_bit <= my_bit_vector(0); when "0000001" => sel_bit <= my_bit_vector(0); . . . when "1111111" => sel_bit <= my_bit_vector(127); when others => null; end process

    FPGA, VHDL & Co. ·Wolle · ·7 Antworten

  • Datei

    VHDL.txt

    segm <= "00000110" when sync = '1' else "00111111"; --Sync-Signal anzeigen segm2<="00000110" when current = '1' else "00111111"; --aktuelles Bit anzeigen TIMER: process(clk, res) begin if res='0' or sig='0' then --Zähler rücksetzen

    in „DCF-Signal auswerten“ · FPGA, VHDL & Co. ·

  • Thread

    Wittig(welec) DSO W20xxA Hardware (Teil 2)

    But when the problem is present, it's there from the start up of the device. When it's still cool...

    our DSO. That can be: - temperture as first candidate for any (temporary) problem - vibrations when moving the device - mechanical forces when turning the range adjusters - mechanical forces when pushing any buttons Temperature as failure source is difficult to proove. Vibrations can be tested

    Mikrocontroller und Digitale Elektronik ·Bruno We · ·681 Antworten

  • Thread

    LUT mit for loop: Synthesefehler

    x"4" => data_out(8*index-1 downto 8*index-8) <= x"34"; when x"5" => data_out(8*index-1 downto 8*index-8) <= x"35"; when x"6" => data_out(8*index-1 downto 8*index-8) <= x"36"; when x"7" => data_out(8*index-1 downto 8*index-8) <= x"37"; when x"8" => data_out(8*index-1 downto 8*index-8) <= x"38"; when x"9" => data_out(8*index-1 downto 8*index-8) <= x"39"; when others => data_out(8*index-1 downto 8*index-8) <= x"30"; end case; end loop; end process; end Verhalten; [/C] Danke schonmal

    FPGA, VHDL & Co. ·T.M. · ·2 Antworten

  • Thread

    VHDL: Reaktion auf Taster

    [/vhdl] mit einer Vorrangigkeit von taster #0; oder eben: [vhdl] case taster_vector is when "001" => do_action1 <= true; when "010" => do_action2 <= true; when "011" => do_action12 <= true; .. when others => null; end case; [/vhdl] In einem anderen process wird entsprechend

    FPGA, VHDL & Co. ·Gregor P. · ·3 Antworten

  • Thread

    5V Schalten mit GPIO 3,3V.

    When Voltage is below 20V and current below 1 Amp, I use the DMC2400 When Voltage is below 30V and 2.8 Amps, I go for DMG56602. Both are in small package and can be ordered at TME.eu. A NP-MOSFET will

    NP-MOS1 is even used as extra protection for 24V / 2.5A powersupplies I developed, to minimize damage when shortcuts occur.

    Analoge Elektronik und Schaltungstechnik ·Marsinator · ·51 Antworten

  • Thread

    Berechnungen in VHDL

    /sample_rate))); when 2 => counter <= (ROUND(2*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(2*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate))); when 3 => counter <= (ROUND(3*(C_S_AXI_ACLK_FREQ_HZ

    sample_rate)-ROUND(15*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate))); when others => counter <= (ROUND(15*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(15*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate))); end case; end process; ... data_sampling_process

    FPGA, VHDL & Co. ·Boris · ·2 Antworten

  • Thread

    umwandlung BCD in Bin

    when "0011" => Bcd <= "011" & ModIn; -- 3*2 + ModIn when "0100" => Bcd <= "100" & ModIn; -- 4*2 + ModIn when "0101" => Bcd <= "000" & ModIn; -- 5*2 + ModIn (ModOut=1)

    (ModOut=1) when "1001" => Bcd <= "100" & ModIn; -- 9*2 + ModIn (ModOut=1) when others => Bcd <= "0000"; end case; end if; end if; end process; ModOut <= '1'

    FPGA, VHDL & Co. ·Alex Alex · ·3 Antworten

  • Datei

    ram_converter_2.vhd

    -- yes, we do a write access sram_wr <= '0'; else -- no, no write access sram_wr <= '1'; end if; when "01" => sram_rd <= '1'; -- write access, hold time sram_wr <= '1'; sram_data <= data_wr; sram_adr <= adr_wr; when "11" => sram_rd <= '0'; -- read access sram_wr <= '1'; sram_data <= (others=>'Z'); sram_adr <= fpga_adr; when others => null; end case; end process; process(fpga_clk) begin if rising_edge(fpga_clk) then tog <= not tog; fpga_di <= sram_data; -- read data register adr_wr <= fpga_adr; -- store for write access

    in „Externens Ram statt FPGA RAM“ · FPGA, VHDL & Co. ·

  • Thread

    I2C-Core von Lattice (RD1005)

    ; when stStartRd => m_state <= stStartWr; --m_state <=stIdle after 1 ns; when others => m_state <=stIdle after 1 ns; end case; end if; end process; scl_pin<='Z' when scl='1' else '0'; sda_pin<= 'Z' when sda='1' else '0'; -------------------------------------- -- tri-state buffer for data bus data <= DATA_OUT when RW_L = '0' else "ZZZZZZZZ

    FPGA, VHDL & Co. ·Thomas · ·2 Antworten

  • Thread

    Aus QFSM generierten vhdl-code compilieren

    next_state <= 3; ELSIF a="1" THEN next_state <= 2; END IF; WHEN 3 => q <= "011"; IF a="0" THEN next_state <= 4; ELSIF a="1" THEN next_state <= 3; END IF; WHEN 4 => q <= "100"; IF a="0" THEN

    next_state <= 1; ELSIF a="1" THEN next_state <= 6; END IF; WHEN OTHERS => null; END CASE; END IF; END PROCESS; END behave;[/vhdl] Kann mich jemand über die Problematik aufklären? In QFSM lässt sich alles ohne Probleme simulieren. Grüsse, Agrippa

    FPGA, VHDL & Co. ·Norbert Fischer · ·2 Antworten

  • Thread

    Fehler beim Kodieren mit vhdl

    N05,N06,A) begin --use Case statement case A is when "001" => COM <= N01; when "010" => COM <= N02; when "011" => COM <= N03; when "100" => COM <= N04; when "101" => COM <= N05; when "110" => COM <= N06; when others => COM <= "ZZZ"; end case; end process; end Behavioral; bin immer nich sicher ob die ICs so parallel die signale multiplezieren

    FPGA, VHDL & Co. ·Eddy Hoffmann · ·7 Antworten

  • Datei

    FIRFilter.vhd

    1) of std_logic_vector(2 * DSIZE - 1 downto 0); -- 48 Bit Akkumulator --signal a_sop : ASOP := ( others => x"000000000000" ); type ASOP is array (0 to NBTAP - 1) of signed(2 * DSIZE - 1 downto 0); -- 48 Bit Akkumulator signal a_sop : ASOP := ( others => x"000000000000" ); type ACOEF is array (0 to NBTAP

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Thread

    sequentieller Addierer mit 32Bit Breite

    result); end addition; Der jeweilige Aufruf dazu: if (blablabla) then case state when 1 => a1_gesamt <= addition (b1, a1_gesamt,'0'); when 2 => a2_gesamt <= addition (b2, a2_gesamt,'0'); ... when 8 => a8_gesamt <= addition (b8, a8_gesamt,'0'); when others =>

    FPGA, VHDL & Co. ·noeppkes · ·11 Antworten

  • Thread

    vhdl anfängerfrage

    process(clk, reset) begin if (reset = '1') then if reset'event then count <= (others => '0') after tpd_reset_to_count; end if; elsif clk'event and (clk = '1') then if (count = "10000111") then count <= "00000000"; else count <= increment

    entity test1; architecture only of test1 is signal count_int : unsigned(7 downto 0) := (others => '0'); function increment(val : unsigned) return unsigned is variable ucount : unsigned(val'range) := val; begin if ucount < 10 then ucount := ucount +

    FPGA, VHDL & Co. ·Michael W. · ·14 Antworten

  • Thread

    Simulation oder Synthese?

    [vhdl] --! This constant provides a means to differ between simulation and synthesis. --! When simulation is active, the constant SIMULATION is TRUE. During --! synthesis, SIMULATION is FALSE. constant SIMULATION : boolean := false -- synthesis translate_off

    function to_integer_f (constant bool : boolean) return integer is begin case bool is when true => return 1; when others => return 0; end case; return 0; end; [/vhdl] ... und zuallerletzt wird, in Abhängigkeit von SIMULATION = true/false, automatisch

    FPGA, VHDL & Co. ·dito · ·16 Antworten

  • Datei

    ps2_mouse.vhdl

    (not ps2_data) = '1') then m2_next_state <= "1010"; else m2_next_state <= "1011"; end if; end if; when "1111" => error_no_ack_Reg <= '1'; m2_next_state <= "1111"; when "1010" => if Resize(bit_count, 7) = "0010110" then m2_next_state <= X"3"; else m2_next_state <= "1010"; end if; when others => m2_next_state

    in „Verilog in VHDL“ · FPGA, VHDL & Co. ·

  • Datei

    sin_gen.vhd

    x"7e", x"7e", x"7e", x"7f", x"7f"); begin Sign_Quadrant <= Sign & Quadrant; case Sign_Quadrant is when "10" => Result_sin2 <= Sinus_Rom ( to_integer(Address)); Data_sin2 <= Result_sin2; when "11" => Result_sin2 <= Sinus_Rom (63-to_integer(Address)); Data_sin2 <= Result_sin2; when "00" => Result_sin2 <= Sinus_Rom ( to_integer(Address)); Data_sin2 <= std_logic_vector (-signed(Result_sin2)); when "01" => Result_sin2 <= Sinus_Rom (63-to_integer(Address)); Data_sin2 <= std_logic_vector (-signed(Result_sin2)); when others => null; end case; if(Quadrant='0') then Result_sin1 <= Sinus_Rom ( to_integer

    in „Frage zur DDFS von Lothar Miller“ · FPGA, VHDL & Co. ·

  • Thread

    VGA Controller mit Krummen und Flimmerndem Bild, Timings scheinen korrekt

    ); end entity; architecture rtl of Counter is signal counter : unsigned(count'range) := (others => '0'); begin process (clk) begin if rising_edge(clk) then if (rst or ov)= '1' then counter <= (others => '0'); elsif load = '1' then counter <= unsigned

    counter <= counter - 1; end if; end if; end if; end process; ov <= '1' when (counter >= MAX and en = '1') else '0'; count <= (count'high downto counter'length => '0') & std_logic_vector(counter); end architecture; [/vhdl] Vielleicht hat mir jemand eine Idee woran es

    FPGA, VHDL & Co. ·Matze · ·10 Antworten

  • Datei

    gen_tick.vhd

    integer:= integer(ceil(log2(real(DVSR-1)))); signal ms_next, ms_reg: unsigned(swidth downto 0) := (others=>'0'); begin -- register process (clk, reset) begin if (reset = '1') then ms_reg <= (others=>'0'); elsif rising_edge(clk) then ms_reg <= ms_next; end if; end process; -- next state logic ms_next <= (others=>'0') when ms_reg=(DVSR-1) else ms_reg + 1; tick <= '1' when ms_reg=(DVSR-1) else '0'; end RTL;

    in „gh_fifo_sync_sr: loadless signals?“ · FPGA, VHDL & Co. ·

  • Thread

    STD_LOGIC_VECTOR Änderung erfassen

    Ohne or_reduce waere: [vhdl] SIG_CHANGED <= '1' when SIG_VERZOGERT /= SIG else '0'; [/vhdl]

    bleibt LOW. Zum überprüfen ob Signal wirklich auf dem Ausgang richtig kommt habe ich auch '0' when ... else '1'; mit else '1' when ... else '0'; und gesehen Ausgang ist jetzt immer HIGH. noch einfache kann man den code nicht mehr gestalten denke ich. kann das Clock welches 200MhZ ist eine rolle

    FPGA, VHDL & Co. ·Alaatdin Özdemir · ·25 Antworten

  • Thread

    unexpected INTEGER LITERAL, expecting IDENTIFIER

    output value if (EN = '1') then -- active high enable pin case SWA is when "00" => LED(0) <= '0'; when "01" => LED(1) <= '0'; when "10" => LED(2) <= '0'; when "11" => LED(3) <= '0'; when others => LED <= "1111";

    FPGA, VHDL & Co. ·Benjamin Hase · ·2 Antworten

  • Datei

    SerialMultiplier.vhd

    partialProduct : std_ulogic_vector(multiplicand'high + 1 downto 0) := (others => '0'); signal lowProductShiftReg : std_ulogic_vector(multiplicator'range) := (others => '0'); signal processingShiftReg : std_ulogic_vector(multiplicator'high + 1 downto 0) := (others => '0'); signal

    in „Signal auf bestimte Range von Port mappen“ · FPGA, VHDL & Co. ·

  • Datei

    Memory_Controller.vhd

    then delay <= delay + 1; else delay <= 0; internal_FPGA_nWE <= '1'; state_reg <= FPGA_wr3; end if; when FPGA_wr3 => if (delay < WAITSTATES) then delay <= delay + 1; else delay <= 0; state_reg <= idle; end if; when FPGA_rd1 => internal_FPGA_nOE <= '0'; internal_RAM_done <= '0'; state_reg <= FPGA_rd2; when

    in „Sram Simulation funktioniert nicht richtig“ · FPGA, VHDL & Co. ·

  • Thread

    TCP/IP Stack Micrchip EEPROM Includen

    on PIC18 devices. The // performance increase of having this option defined is only apparent when // the HTTP server is servicing multiple connections simultaneously. //#define HTTP_SAVE_CONTEXT_IN_PIC_RAM // Indicate what file to serve when no specific one is requested #define HTTP_DEFAULT_FILE

    pin on Explorer 16 schematic // remapped and actually connected to PIC24FJ256GB210 pin 90 (RG0) when // JP1 on PIM has pins 1-2 shorted (USB). When JP1 pins 2-3 are shorted // (PMP), PIC pin 90 does connect to RD12. To make the PIM work with // either jumper setting, we will drive both

    Mikrocontroller und Digitale Elektronik ·sven · ·11 Antworten

  • Datei

    top.vhd

    <= startup; end if; when startup => debug <= NOT "01100000"; --debug <= NOT std_logic_vector(to_unsigned(state_t'pos(status),8)); if (delay <= CLOCK) then delay <= delay + 1; status <= startup; else status <= running; end if; when running => debug <= NOT "00011100"; --debug <= NOT std_logic_vector(to_unsigned(state_t'pos(status),8)); status <= running; when others => debug <= NOT "00000001"; --debug <= NOT std_logic_vector(to_unsigned

    in „Statemachine springt in falsche "states" warum?“ · FPGA, VHDL & Co. ·

  • Thread

    Tri-State Element für Spratan3(Xilinx)

    begin if en = '1' then i_o <= out_i; else i_o <= (others => 'Z'); end if; end process WRITE; -- paralleler Lesevorgang READ: in_i <= i_o; end Behavioral; werde das ganze mal simulieren, danach werde ich wohl klüger...

    Einfacher und besser ist vielleicht : i_o <= out_i when en = 1 else (others => 'Z'); in_i <= i_o; und die entity wegläßt, indem Du diese 2 Zeilen ins Top-Level schreibst.

    FPGA, VHDL & Co. ·Juri · ·7 Antworten

  • Datei

    ether_speed.vhd

    speed_detect; architecture behavioral of speed_detect is signal countertx: unsigned (2 downto 0):=(others=>'0'); signal counterrx : unsigned (2 downto 0):=(others=>'0'); begin -- here is testing if GMII aktive or not? -- algorithm -- in GMII RX-clk has 125MHz -- Now the question run RX-clk in with a higher

    in „VHDL timing in GMII auf Spartan6“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL inout Problem

    ; process(READ_DATA, DATA_OUT) begin if READ_DATA = '1' then DATA_INOUT <= ( others => 'Z' ); DATA_IN <= DATA_INOUT; else DATA_INOUT <= DATA_OUT; end if; end process; end Behavioral; [/code] Wenn ich das nun hiermit simuliere, dann geht DATA_INOUT

    concurrent machen, etwa in dieser Art: [vhdl] DATA_IN <= DATA_INOUT; DATA_INOUT <= 'Z' when READ_DATA = '1' else DATA_OUT; [/vhdl]

    FPGA, VHDL & Co. ·Pit · ·8 Antworten

  • Thread

    HEX-Anzeige mit Ansteuerung+zwei kleine Fragen zu VHDL, ALTERA DE1 board

    DISPLAY AB HIER----- ---------HEX1-------------------- WITH RESULT SELECT HEXD1 <= "0111111" WHEN "00000",---0 "0000110" WHEN "00001",---1 "1011011" WHEN "00010",---2 "1001111" WHEN "00011",---3 "1100110" WHEN "00100",---4 "1101101" WHEN "00101",---5 "1111101" WHEN "00110",---6 "0000111" WHEN "00111",---7 "1111111" WHEN "01000",---8 "1101111" WHEN "01001",---9 "0111111" WHEN "01010",---10 "1111001" WHEN OTHERS;--- Error H0 <= NOT HEXD1(0); H1 <= NOT HEXD1(1); H2 <= NOT

    FPGA, VHDL & Co. ·GS · ·2 Antworten

  • Thread

    SPI übertragungsablauf

    void spi_init() // Initialize pins for spi communication { /* Set MOSI SCK and SS output, all others input */ DDR_SPI = ((1 << DD_MOSI) | (1 << DD_SCK) | (1 << DD_SS)); PORT_SPI |= (1 << DD_SS); DDR_SPI &= ~(1 << DD_MISO); /* Enable SP */ SPCR = ((1<<SPE)| // SPI Enable

    SPR0)| // SPI Clock Rate (0<<CPOL)| // Clock Polarity (0:SCK low / 1:SCK hi when idle) (0<<CPHA)); // Clock Phase (0:leading / 1:trailing edge sampling) } uint8_t spi_fast_shift (uint8_t data) // Clocks only one byte to target device and returns the received

    Mikrocontroller und Digitale Elektronik ·Kimmy · ·35 Antworten

  • Thread

    UART Transmitter, FSM

    0; state_next <= start_transmit; end if; when start_transmit => tx <= '0'; count_next <= count_reg + 1; if count_reg = n-1 then count_next <= 0; state_next <= data_transmit; end if; when data_transmit => count_next <= count_reg + 1; tx <= data_reg(dbits_reg); if count_reg = n-1 then count_next <= 0; dbits_next <= dbits_reg + 1;

    FPGA, VHDL & Co. ·Daniel -------- · ·5 Antworten