Suchergebnisse für "high low"

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LM2574.pdf

drive this pin with a “high-frequency,” “low-inductance,” or “low-ESR.” These will high-level TTL or CMOS signal. The ON /OFF pin can be reduce the output ripple to 10 mV or 20 mV. However, when safely pulled up to +V IN without

in „Iverting Buck Boost -5V“ · Analoge Elektronik und Schaltungstechnik · 15.04.2010 15:44

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AN-1148.pdf

will be illustrated using very high frequency. these assumptions: The NPN regulator uses a technique called dominant pole At maximum load current, the load pole (P L) occurs at a compensation because it has no inherent low-frequency frequency

in „PIC, Platine, geht das so?“ · Mikrocontroller und Digitale Elektronik · 09.01.2007 19:42

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AN-1148.pdf

will be illustrated using very high frequency. these assumptions: The NPN regulator uses a technique called dominant pole At maximum load current, the load pole (P L) occurs at a compensation because it has no inherent low-frequency frequency

in „AC-Störung auf +15Vdc“ · Mikrocontroller und Digitale Elektronik · 23.11.2007 15:02

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M48Z02.pdf

Min Max Min Max Min Max t WRITE cycle time 70 150 200 ns AVAV tAVWL Address valid to WRITE enable low 0 0 0 ns tAVEL Address valid to chip enable 1 low 0 0 0 ns WLWH WRITE enable pulse width 50 90 120 ns tELEH Chip enable low to chip enable 1 high 55 90 120 ns WHAX WRITE enable high to address transition

in „[S] DALLAS DS1220Y-150 NVRAM (NOS)“ · Analoge Elektronik und Schaltungstechnik · 12.02.2026 22:15

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20002234D.pdf

from a low 0.65V input. High efficiency is accomplished 3.3V OUT @ 1 mA by integrating the low resistance N-Channel Boost • Adjustable Output Voltage Range: 2.0V to 5.5V switch and synchronous P-Channel switch

in „NRF24L01+ durch MCP1640 gestört?“ · Mikrocontroller und Digitale Elektronik · 23.08.2021 20:36

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HEF40174B_CNV_3-85044.pdf

master reset input (MR), and six(O0to O 5 LOW) independent of CP and D t0 D . 5 Fig.1 Functional diagram. PINNING D0to D 5 data inputs CP clock input (LOW to HIGH; edge-triggered) MR master reset input (active LOW) O 0o O 5 buffered outputs FUNCTION

in „[V] 50St. Latches Philips HEF40174BT SO16 HEX ”D” – TYPE FLIP–FLOP“ · Markt · 15.04.2022 13:16

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HEF40174B_CNV_3-85044.pdf

master reset input (MR), and six(O0to O 5 LOW) independent of CP and D t0 D . 5 Fig.1 Functional diagram. PINNING D0to D 5 data inputs CP clock input (LOW to HIGH; edge-triggered) MR master reset input (active LOW) O 0o O 5 buffered outputs FUNCTION

in „[V] 70St. HEF40174 Latch SMD“ · Markt · 13.06.2021 20:26

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HEF40174B.pdf

master reset input (MR), and six(O0to O 5 LOW) independent of CP and D t0 D . 5 Fig.1 Functional diagram. PINNING D0to D 5 data inputs CP clock input (LOW to HIGH; edge-triggered) MR master reset input (active LOW) O 0o O 5 buffered outputs FUNCTION

in „[V] 70St. HEF40174 Latch SMD“ · Markt · 13.06.2021 20:30

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MC10EP31-D.PDF

2480 2215 2540 mV VIL Input LOW Voltage (Single-Ended) 1365 1690 1430 1755 1490 1815 mV IIH Input HIGH Current 150 150 150 mA IIL Input LOW Current 0.5 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium

in „Rechtecksignal mit Anstiegszeit < 1 ns für Oszi- und Tastkopf-Tests“ · HF, Funk und Felder · 19.11.2019 19:35

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as7c1024bv_2.0-1265254.pdf

(OE) access timt - 5 – 6 – 7 – 8 ns OE Output hold from address changOHt 3 - 3 – 3 – 3 – ns 5 CE1 Low to output in low Z tCLZ1 3 - 3 – 3 – 3 – ns 4, 5, 12 CE2 High to output in low Z tCLZ2 3 - 3 – 3 – 3 – ns 4, 5, 12 CE1 Low to output in high Z tCHZ1 - 4 – 5 – 6 – 7 ns 4, 5, 12 CE2 Low to output in high Z t - 4 – 5 – 6 – 7 ns 4, 5, 12 CHZ2 OE Low to output in low Z tOLZ 0 - 0 – 0 – 0 – ns 4, 5 OE High to output in high Z t – 4 – 5 – 6 – 7 ns 4, 5 OHZ Power up time tPU 0 - 0 – 0 – 0 – ns 4, 5, 12 Power

in „[V] 7St. SRAM Alliance AS7C1024B-12TCN 128K*8 12ns 3V“ · Markt · 21.08.2021 23:12

Datei

20221003a-Einspeise.ino

); if(!drain) { drainist = millis(); if(drainist - drainstart > drainvz) { ovlodrain = LOW; } } else { drainstart = millis(); ovlodrain = HIGH; } // UVLO Batteriespannung (bei Unterspannung HIGH) batt = (analogRead(battpin) > battwert); if(!batt) { uvlobatt = HIGH; battwert = battwerthoch

in „Eigenbau Einspeisewechselrichter“ · Haus & Smart Home · 03.10.2022 20:30

Datei

Programm_-_Mobiler_Roboter.asm

WAIT_1s rcall rechtskurve rcall WAIT_1s rcall stop rcall WAIT_1s rjmp main geradeaus: ldi temp1, HIGH(600) sts OCR1AH, temp1 ldi temp1, LOW(600) sts OCR1AL, temp1 ldi temp1, HIGH(600) sts OCR1BH, temp1 ldi temp1, LOW(600) sts OCR1BL, temp1 ret stop: ldi temp1, HIGH(0) sts OCR1AH, temp1 ldi temp1, LOW

in „Mobiler Roboter- Assembler- Atmega 48- AVR studio 4“ · Mikrocontroller und Digitale Elektronik · 06.10.2011 20:38

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CN0276.pdf

/CN0276. Ultralow Power, 3-Lead, SOT-23 ADM6328 Microprocessor Reset Circuits ADP7104 20V, 500 mA, Low Noise, CMOS LDO AD8692/ Low Cost, Low Noise, Dual/Quad CMOS, AD8694 RRO Op Amps High Performance,10-Bit to 16-Bit Resolver-to-Digital Converter EVALUATION AND DESIGN SUPPORT CIRCUIT FUNCTION ANDBENEFITS

in „Resolver converter Amplitude“ · Analoge Elektronik und Schaltungstechnik · 04.01.2024 20:46

Datei

LCD-Routine2_MC2.inc

..:: Function-Set LDI Temp, 0b00000010 OUT LCD_PORT, Temp SBI LCD_PORT, LCD_E // Enable-Bit auf HIGH gesetzt. NOP // Takte abwarten bevor wieder auf LOW geschaltet wird. NOP NOP NOP NOP CBI LCD_PORT, LCD_E // Enable-Bit auf LOW gesetzt. Befehl ausgeführt. RCALL Delay_5ms // Wartezeit von 50 µs. //

in „LCD macht nicht was es soll trotz Tutorial.“ · Mikrocontroller und Digitale Elektronik · 12.08.2013 13:17

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HDD_Quantum.pdf

na Sector Number Sector Number or LBA Cylinder Low Cylinder low or LBA Cylinder High Cylinder high or LBA Device/ Head obs Na obs DEV HEAD number or LBA Status BSY DRDY DF DSC DRQ na na ERR Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT 6-33

in „HDD Festplatte ATA IDE an AVR µC Mikrocontroller ATmega1284p Assembler - viele Fragen“ · Mikrocontroller und Digitale Elektronik · 16.04.2018 22:14

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ADC08L060.pdf

Reference Ladder Current VRT to VRB 2.2 2.7 mA CLK, PD DIGITAL INPUT CHARACTERISTICS VIH Logical High Input Voltage V DR = VA= 3.6V 2.0 V (min) VIL Logical Low Input Voltage V DR = VA= 2.7V 0.8 V (max) I Logical High Input Current V = V = V = 3.6V 10 nA IH IH DR A IL Logical Low Input Current V IL0V

in „Digitales Oszi im Selbstbau“ · Mikrocontroller und Digitale Elektronik · 11.10.2006 12:23

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LT1734.pdf

2 LTC1734L 6 50mA LOW HIGH OPTIONAL FILTER GND DRIVE FZT549 125mA HIGH LOW CHARGE CHARGE IBAT 175mA HIGH HIGH CURRENT 1k PIN 4 CURRENT 4 PROG BAT 5 MONITOR MONITOR SINGLE (FILTERED) 0.5µF TO (UNFILTERED) 3k 7.5k 10µF Li-Ion

in „akku mit solar aufladen, kommt das IC: LT1734L dafür in Frage?“ · Analoge Elektronik und Schaltungstechnik · 16.02.2011 12:20

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3971fd.pdf

operationisthatsmallerinductorandcapacitorvaluesmay 1− fSW OFF(MIN) be used. The disadvantages are lower efficiency, lower where V IN(MIN) is the minimum input voltage, V OUT is maximuminputvoltage,andhigherdropoutvoltage.The the output voltage, V is the catch diode drop (~0.5V), highest acceptable switching

in „[V] LT3971IDD-5PBF-ND“ · Markt · 21.04.2022 06:35

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tps63020.pdf

EN, PS/SYNC input low voltage 0.4 V VIH EN, PS/SYNC input high voltage 1.2 V EN, PS/SYNC input current Clamped to GND or VINA 0.01 0.1 μA PG output low voltage V = 3.3 V, I = 10 μA 0.04 0.4 V OUT PGL PG output leakage current

in „ESP32-H2 will nicht schlafen“ · Mikrocontroller und Digitale Elektronik · 28.12.2025 10:05

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Control_Loop_Design_SLUP098__TI.pdf

minimize offset error delays of slope associated with a single pole, the gain does not rise rapidly at lower frequencies. The lower compensation capacitors in thefeedback path. Control Loop Basics The control loop in a high perfonnance switching power supply requires high gain, to achieve good regulation,

in „SG3524 bleibende Regelabweichung“ · Analoge Elektronik und Schaltungstechnik · 26.07.2014 18:27

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Suchergebnisse für "high low"

18429 Treffer für high low Suchergebnisse für "high low"

18429 Treffer für high low