Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Datei

    AVGA.txt

    '; else VSync <= '1'; end if; end if; end if; end process; Data <= SRAM_Data; SRAM_Data <= AVR_AD when Clock = '0' and AVR_WR = '0' and Reset = '1' else (others => 'Z'); SRAM_Addr <= (others => 'Z') when Reset = '0' else Addr when Clock = '1' else "000" & AVR_AH & Latch when AVR_AH(7) = '0' else Bank

    in „VHDL Integer Counter“ · FPGA, VHDL & Co. ·

  • Datei

    CIC4Stage_SM.vhd

    -- 2^16 -- when x"020000" => nShift <= 68; -- 2^17 -- when x"040000" => nShift <= 72; -- 2^18 when others => nShift <= 0; end case; end if; end process Decimation; Integrator : process(nReset, iClk) begin if (nReset

    in „CIC Additionsknoten“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL / case

    BEGIN p1: PROCESS (i,a,b,c) BEGIN -- alle Zweige sind gleichwertig CASE i IS WHEN 3 => z <= a; WHEN 0 TO 2 => z <= b; WHEN OTHERS => z <= c; END CASE; END PROCESS p1; END case_variante;

    p1: PROCESS (i,a,b,c) > BEGIN > -- alle Zweige sind gleichwertig > CASE i IS > WHEN 3 => z <= a; > WHEN 0 TO 2 => z <= b; > WHEN OTHERS => z <= c; > END CASE; > END PROCESS p1; > > END case_variante; genau das wurde mir bei der Klausur angestrichen.

    FPGA, VHDL & Co. ·Mathias B. · ·11 Antworten

  • Thread

    Allererster Versuch - Frequenzteiler

    2µs when "0111" => count_to <= 100; --div by 200 -> 5µs when others => count_to <= 1; end case; end process; process begin wait until rising_edge(clk); if

    80 -> 2µs when "0111" => count_to <= 100-1; --div by 200 -> 5µs when others => count_to <= 1-1; end case; end process; process begin wait until rising_edge(clk);

    FPGA, VHDL & Co. ·Norbert S. · ·41 Antworten

  • Thread

    Schleifen in Zustandsmaschinen

    und Daten zuweisen -- address_key <= (others => '0'); address_key <= std_logic_vector(to_unsigned(n,8)); data_in_key <= key_in; load_key_state <= one; when one => -- Adresse inkrementieren n := n + 1;

    abgeschlossen done <= '1'; -- Ende load_key_state <= two; end if; when two => null; end case;

    FPGA, VHDL & Co. ·Hans-Werner · ·16 Antworten

  • Thread

    Wartezustand in Zustandsautomat

    when others => next_state <= st_standby; end case; end process; end Behavioral; Die eingangsseitige Clock läuft mit 3.125 MHz. k1 wird in einem anderen Modul dann über

    state, button_down, switch_reg) >begin > if (state = st_k1) then > case button_down(0) is > when '1' => k1_i <= k1_i+1; > when others => k1_i <= k1_i; > end case; > end if; >end process; Hier stecken zwei Fehler drin. 1.) Welchen Wert bekommt k1_i wenn state= st_k1 nicht erfüllt

    FPGA, VHDL & Co. ·Johannes Ruder · ·12 Antworten

  • Datei

    CF_SM.vhd

    (22); when "11" => leds (3) <= '1'; when others => null; end case; case (data_in_buffer (9 downto 8)) is when "00" => leds (2) <= '0'; when "01" => leds (2) <= blink_counter (25); when "10" => leds (2) <= blink_counter

    in „Immer noch Kompaktblitz“ · FPGA, VHDL & Co. ·

  • Thread

    Multiplexer aus std_logic

    habe eine Multiplexer Beschreibung folgender Art gefunden: [vhdl] (...) CASE sel IS WHEN "00" => output <= in0; WHEN "01" => output <= in1; WHEN "10" => output <= in2; WHEN "11" => output <= in3; WHEN OTHERS => output <= 'X'; END CASE; (...) [/vhdl] Meine Frage ist nach dem when others. Macht eine solche Beschreibung Sinn, oder wäre es aureichend when "11" durch when others zu ersetzen? schöne grüße

    FPGA, VHDL & Co. ·Fandango · ·1 Antworten

  • Thread

    Hilfsprogramm zur ROM-Erzeugung geschrieben

    -> ROM byte range [0xa, 0xe] 11 => x"01", 12 => x"02", 13 => x"03", 14 => x"04", others => x"ff"); begin process (Clk) begin if falling_edge(Clk) then Dint <= ROMdata(to_integer(unsigned(A))); end if; end process; D <= Dint when OE_n='0' else (others => 'Z');

    14 => x"06", 15 => x"00", 16 => x"3c", 17 => x"c3", 18 => x"02", 19 => x"00", others => x"ff"); begin process (A) begin Dint <= ROMdata(to_integer(unsigned(A))); end process; D <= Dint when OE_n='0' else (others => 'Z'); end BEHAVIOR; [/vhdl]

    FPGA, VHDL & Co. ·Rüdiger Knörig · ·17 Antworten

  • Datei

    CIC4Stage.vhd

    -- 2^16 -- when x"020000" => nShift <= 68; -- 2^17 -- when x"040000" => nShift <= 72; -- 2^18 when others => nShift <= 0; end case; end if; end process Decimation; Integrator : process(nReset, iClk) begin if (nReset

    in „CIC Additionsknoten“ · FPGA, VHDL & Co. ·

  • Datei

    HW1Bsp3.vhd

    ', d => '1', others => '0'); when 3 => return (a => '1', b => '1', g => '1', c => '1', d => '1', others => '0'); when 4 => return (b => '1', c => '1', g => '1', f => '1', others => '0'); when 5 => return (a => '1', f => '1', g => '1', c => '1', d => '1', others => '0'); when 6 => return (a => '1', c => '1', d => '1', e => '1', f => '1', g => '1', others => '0'); when 7 => return (a => '1', b => '1', c => '1', others => '0'); when 8 => return (a => '1', b

    in „Vhdl Anfänger Code Analyse“ · FPGA, VHDL & Co. ·

  • Thread

    Finite-State-Machine

    <= STOP ; end if ; when STOP => if (A xor B)=`1` then NEXTSTATE <= START ; end if ; when others => NEXTSTATE <= START ; end case ; end process

    <= STOP ; end if ; when STOP => if (A xor B)=`1` then NEXTSTATE <= START ; end if ; when others => NEXTSTATE <= START ; end case ; end process

    FPGA, VHDL & Co. ·VHDL-Beginner · ·5 Antworten

  • Thread

    XC9572XL als GLCD-Treiber mit Stabilitätsschwäche. Code-Problem? EMV? Defekt?

    Verhalten konnte ich bis auf in etwa das hier reduziert beobachten: [vhdl] begin c_da <= (others => '0') when c_we = '1' and c_oe = '0' else (others => 'Z'); process begin wait until rising_edge(clk); -- !!! wait until rising_edge(clk); d_flm <= '1';

    die geringe Menge an FFs. Ich meinte, das wäre insofern im gelben Bereich: [vhdl] c_da <= c_d when c_oe = '0' and c_we = '1' else (others => 'Z'); m_d <= c_d when writing else (others => 'Z'); m_we <= '0' when writing else '1'; [/vhdl] writing und c_d werden synchron gesetzt. c_oe ist asynchron

    FPGA, VHDL & Co. ·Malte S. · ·12 Antworten

  • Thread

    Ausgangssignal eines FPGA basierten Tiefpasses

    begin if (rising_edge(clk)) then case (current_state) is when waitForADC => filter_rdy_intern <= '0'; data_read_ready <= '0'; sop := (others => '0'); counter_filter := 0;

    case (current_state) is --Alles zurücksetzen when startup => result := (others => '0'); temp_result := (others => '0'); counter_filter := 0;

    Digitale Signalverarbeitung / DSP / Machine Learning ·Alex K. · ·35 Antworten

  • Thread

    VHDL RAM Ansteuerung

    --------------- -- -- RamWrite Low --------------------------------------------- -- when Z6 => F_ZUSTAND <= Z0; -- ---------------------------------------------------------- -- -- Others---------------------------------------------------- -- when others => null;

    - In Abhängigkeit des Counters when 0 => IDATA(7 downto 0)<= DAT_IN; -- die Postions vergeben when 1 => IDATA(15 downto 8)<= DAT_IN; when 2 => IDATA(23 downto 16)<= DAT_IN; when others

    FPGA, VHDL & Co. ·Reni · ·4 Antworten

  • Thread

    Rechnen mit signed und unsigned

    end Broke; architecture verhalten of Broke is begin with cardsum select broke <= '1' when "10110", '1' when "10111", '1' when "11000", '1' when "11001", '1' when "11010", '1' when "11011", '1' when "11100", '1' when "11101", '1' when "11110", '1' when "11111", '0'when others; end verhalten; [/vhdl] Das ginge so viel kürzer: [vhdl] port( cardsum:in std_logic_vector(4 downto 0) broke

    FPGA, VHDL & Co. ·Anfänger · ·8 Antworten

  • Thread

    Process wird kontinuierlich durchloffen - Altium LiveDesign Board

    x"71" => usignal <= "1101"; zeichen <= '1'; -- ENTF(,) when x"66" => usignal <= "1110"; zeichen <= '1'; -- BACKSPACE when others => usignal <= "1111"; zeichen <= '1'; -- ERROR end case; else test <= '0'; END IF; END PROCESS; Process

    downto 0) <= wert1(3 downto 0); zustand <= x"03"; end if; when x"03" => zustand <= x"03"; when others => zustand <= x"FF"; -- ERROR end case; end if; end if; END Process; -- Ausgabe hier weggelassen end Behavioral; [/vhdl]

    FPGA, VHDL & Co. ·Daniel Schindler · ·34 Antworten

  • Thread

    Bitstrom per Huffman-Tabelle erzeugen

    when "11"=> rot_buffer(31 downto 24) <=input_reg(15 downto 8); when others=> null; end case; end if; end if; end if; end if; end process; process (barrel_pointer,rot_buffer)

    30 downto 15); when 31 => barrel<= rot_buffer (31 downto 16); when others => null; end case; end process; [/vhdl]

    FPGA, VHDL & Co. ·Cihan Kalayci · ·44 Antworten

  • Thread

    Problem mit LPT unter WinNT,Win200, WinXP

    -------------------- Configuration Register B, like Configuration Register A is only available when the ECP Port is in Configuration Mode. When in this mode, cnfgB resides at Base + 401h. Below is the make-up of the cnfgB Register. Bit(s) Function 7 1 Compress outgoing Data Using RLE 0 Do

    ports may be software configurable, where you can set the IRQ and DMA resources from the register. Others may be set via BIOS or by using jumpers on the Card, thus are read only. Bit 7 of the cnfgB Register selects whether to compress outgoing data using RLE (Run Length Encoding.) When Set, the host

    Softwareentwicklung ·Fix · ·39 Antworten

  • Datei

    rechner.vhdl

    -------------------- when XODER => ausgabe(15 downto 0) <= wert1(15 downto 0) xor wert2(15 downto 0); ausgabe(19 downto 16) <= "0000"; vorzeichen <= '0'; zustand <= ERG; when others => zustand <= ERROR; end case; when "0100"

    in „Process wird kontinuierlich durchloffen - Altium LiveDesign Board“ · FPGA, VHDL & Co. ·

  • Thread

    SJA1000 ansteuern?

    Adresse begonnen wird) StateMachine := -1; -- Abarbeitung beenden when others => -- Zu allen anderen Zeitpunkten... null; -- ...nichts unternehmen end case; -- StateMachine

    Adresse begonnen wird) StateMachine := -1; -- Abarbeitung beenden when others => -- Zu allen anderen Zeitpunkten... null; -- ...nichts unternehmen end case; -- StateMachine

    FPGA, VHDL & Co. ·Steffen Hausinger · ·32 Antworten

  • Thread

    Asynchrone SRAM Controller mit Waitstate

    state_next <= rd1; end if; end if; ready <= '1'; when wr1 => state_next <= wr2; when wr2 => state_next <= idle; when rd1 => state_next <= rd2; when rd2=> data_s2f_next <=

    o for SRAM chip a ce_a_n <='0'; ub_a_n <='0'; lb_a_n <='0'; dio_a <= data_f2s_reg when tri_reg='0' else (others=>'Z'); end arch; Meine Frage lauten: 1) sieht mein SRAM Controller(FSM) funktionsfähig aus da ich nicht zum Laufen bringen konnte? 2) Wie soll ich dann 6 Waitstate

    FPGA, VHDL & Co. ·Keller Thomas · ·5 Antworten

  • Thread

    Hall Sensor in VHDL/FPGA

    when others => BCD_OUT <= "1110"; end case; end process; end arch; [/vhdl] [vhdl] LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BCD_TO

    "1000" => a <= '0'; b <= '0'; c <= '0'; d <= '0'; e <= '0'; f <= '0'; g <= '0'; when "1001" => a <= '0'; b <= '0'; c <= '0'; d <= '0'; e <= '1'; f <= '0'; g <= '0'; when others => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '1'; f <= '1'; g <= '0'; end case

    FPGA, VHDL & Co. ·Wolfgang · ·19 Antworten

  • Thread

    INOUT immer im 'U' Zustand

    std_logic := '1'; SIGNAL hlt: std_ulogic := '0'; SIGNAL dbus: std_logic_vector(7 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL rsel: std_logic_vector(4 DOWNTO 0) := (OTHERS => 'Z'); BEGIN u1: asic PORT MAP(reset, clk, cs, rd, wr, int, dbus, rsel); .... PROCEDURE ReadSCR(val: OUT byte

    Das [vhdl] clk <= '1' AFTER tcyc/2 WHEN (clk='0' AND hlt='0') ELSE '0' AFTER tcyc/2; [/vhdl] wäre so etwas kompakter und übersichtlicher: [vhdl] clk <= not clk AFTER tcyc/2 WHEN (hlt='0') ELSE '0'; [/vhdl] Aber sei's drum ;-)

    FPGA, VHDL & Co. ·Markus K. · ·18 Antworten

  • Thread

    Problem mit counter

    rechteck <= '0'; when "110" => rechteck <= '0'; when "111" => rechteck <= '0'; when others => end case; end process; ENTITY count IS PORT ( clock: IN STD_LOGIC; result: OUT

    Deine Statemaschine hat 9 Zustände. keine Ahnung, ich vermute mal, dass Du statt# when "111" => rechteck <= '0'; when others => end case; einfach when others => rechteck <= '0'; end case; schreiben solltest Gruß Kest

    FPGA, VHDL & Co. ·Mattias · ·7 Antworten

  • Thread

    Signalwertzuweisung zu spät

    0001"; elsif row_buttons_i <= "1111" then s_pressed_button <= (others => '0'); end if; when "1101" => if row_buttons_i(0) = '0' then s_pressed_button <= s_pressed_button or X"0004"; elsif

    2000"; elsif row_buttons_i <= "1111" then s_pressed_button <= (others => '0'); end if; when others => s_pressed_button <= (others => '0'); end case; end if; end if; end process; pressed_button_o

    FPGA, VHDL & Co. ·Johannes H. · ·5 Antworten

  • Thread

    Verilog Ausdruck "(| OOPS)" in VHDL

    Auswertung machen. Generisch würde man das in VHDL in etwa so schreiben: [vhdl] BACK_UP <= '1' when (OOPS != (others => '0')) and STATE = OOPS_S else '0'; [/vhdl] Gruß Marcus

    deinem VHDL Code muss ich dich leider berichtigen: Ungleich ist in VHDL "/=" nicht "!=", und (others => '0') darf nur bei einer Zuweisung verwendet werden, aber nicht bei einer Abfrage. Man könnte es dann so schreiben: [VHDL] BACK_UP <= '1' when (OOPS /= conv_std_logic_vector(0,OOPS'length

    FPGA, VHDL & Co. ·Guest · ·7 Antworten

  • Datei

    sdram_access.vhd

    <= '1'; rcas <= '1'; rwe <= '1'; rba <= (others => '0'); radr <= (others => '0'); when CMD_NOP => rcs <= '0'; rras <= '1'; rcas <= '1'; rwe <= '1'; when CMD_ACTIVE => rcs <= '0'; rras <= '0'; rcas <= '1'; rwe <= '1'; rba <= SDRAM_Addr (22 downto

    in „Frage zu SDRAM“ · FPGA, VHDL & Co. ·

  • Thread

    Multiplexer 5x2 in VHDL

    with s select y <= "00" when "000", "01" when "001", ... "11" when "111"; > Ich bekomme das einfach nicht auf die Kette. Du bist nur faul!

    with SEL select Y1 <= a(0) when "100", a(1) when "010", a(2) when "111", '0' when others; Y2 <= a(2) when "111", '0' when others; LED1 <= Y1; LED2 <= Y2;

    FPGA, VHDL & Co. ·Stefan M. · ·5 Antworten

  • Thread

    Bitfolge getriggert ausgeben

    std_logic_vector(63 downto 0) := x"1234567890abcdef"; signal sr_pattern : std_logic_vector(63 downto 0) : (others => '1'); signal sr_trigger : std_logic_vector(2 downto 0) : (others => '0'); : -- Trigger für Flankenerkennung einsynchronisieren sr_trigger <= sr_trigger(1 downto 0) & in_trigger when rising_edge

    Mark W. schrieb im Beitrag #5706996: > signal sr_pattern : std_logic_vector(63 downto 0) : (others => '1'); > signal trigger : std_logic : '0'; Ja, da fehlen wohl noch 2 '=' Zeichen. Aber keine Sorge, du findest den richtigen Platz. Einfach mal die Zeile drüber oder drunter anschauen... ;-)

    FPGA, VHDL & Co. ·Mark W. · ·17 Antworten

  • Thread

    Mittelwertbildung aus 16 16-Bit-Worten

    end if; end process; process (state) begin nextstate <= state; case state is when "00" => -- I2C-Bus Initialisieren ... when "01" => -- lesen vom I2C-Bus ... when "10" => -- MW-Bildung enable <= '1'; -- enable-signal für MW

    -- zuweisen nextstate <= "11"; end if; when "11" => -- senden auf I2C-Bus when others => nextstate <= "00"; end case; end process; Ich bin nun schon seit einigen Wochen dran und schaffe es einfach nicht. Es ist zum verzweifeln

    FPGA, VHDL & Co. ·Andi · ·15 Antworten

  • Thread

    mehere Archi/Entity

    ------------------- srctr_idle_p: process (state) begin case state is when FSM_IDLE|FSM_WRITE_MEM_3|FSM_READ_MEM_3 => srctr_idle_o <= '1'; --activate the idle-output signal when others => srctr_idle_o <= '0'; --deactivate the idle-output signal end

    ) <= to_stdlogicvector(data_reg(7 downto 0)); --transfer data_reg byte0 to mem_data_b byte1 when others => mem_data_b <= (others => 'Z'); --high impedance if not in Write-Mode end case; end process data_b_p ;

    FPGA, VHDL & Co. ·Crouch · ·1 Antworten

  • Thread

    signal zwar in simulation, aber nicht auf hardware

    hier mal ein auszug des codes: [vhdl] with ram_sw_i select wr_adr_a <= std_logic_vector(wr_adr_i) when '0', "00000" when others; with ram_sw_i select wr_adr_b <= std_logic_vector(wr_adr_i) when '1', "00000" when others; with ram_sw_i select wr_enable_a <= wr_en_i when '0', '0' when others; with ram_sw_i select wr_enable_b <= wr_en_i when '1', '0' when others; [/vhdl] jo ich kanns mir nicht erklären. es sollte ja eigentlich am pin anliegen. kann mir da jemand weiterhelfen? mfg Andi

    FPGA, VHDL & Co. ·Andi Z. · ·3 Antworten

  • Thread

    Ablauf von einer Programmänderung mit Quartus2

    begin if rising_edge(clk) then if terminal_count = '1' then case state is when "01" => state <= "10"; when "10" => state <= "01"; when others => state <= "01"; end case; end if; end if; end process

    case state is when "01" => state <= "10"; when "10" => state <= "01"; when others => state <= "01"; end case

    FPGA, VHDL & Co. ·Peter B. · ·8 Antworten

  • Thread

    VHDL-SPI implementierung

    Laenge --> alle Bits uebertragen signal tx_reg : std_logic_vector(Laenge-1 downto 0) := (others=>'0'); signal rx_reg : std_logic_vector(Laenge-1 downto 0) := (others=>'0'); begin ------ Verwaltung -------- process begin wait until rising_edge(CLK); MOSI <= tx_reg

    : : proces begin wait until rising_edge(clk); case state is when IDLE => if ... then : : state <= CALC; end if; when CALC => : : when READY => state <= IDLE; end

    FPGA, VHDL & Co. ·VHDL-Frage · ·26 Antworten

  • Thread

    UART + Xilinx + Altera

    tx_ready <= '0'; Tx <= '1'; case count_bit is when 0 => Tx <= '0'; count_bit <= count_bit + 1; when 9 => Tx <= '1'; count_bit <= count_bit + 1; when 10 => Tx <= '1'; count_bit <= 0; sent <= true; tx_ready <= '1'; when others => count_bit <= count_bit

    FPGA, VHDL & Co. ·Daniel R. · ·25 Antworten

  • Thread

    Multiplexer - SD Card - Richtung

    std_logic_vector (8 downto 0); data_ext: InOut std_logic_vector (8 downto 0); case select is when '1' => data_fpga<=data_sd; data_ext<= (others=>'Z'); -- hochohmig when '0' => data_fpga<=(others=>'Z'); -- hochohmig data_ext<= data_sd; end case; Danke

    Datenleitungen sind bidirektional, oder? Dann wäre das hier richtig: [vhdl] case select is when '1' => data_fpga<=data_sd; data_sd<=data_fpga; data_ext<= (others=>'Z'); -- hochohmig when '0' => data_fpga<=(others=>'Z'); -- hochohmig data_ext<= data_sd; data_sd

    FPGA, VHDL & Co. ·Nik Nn · ·11 Antworten

  • Datei

    EM4095_Reader.vhd

    1'; elsif ((row_parity_error > 1) or (col_parity_error > 1)) then debug_signal(6) <= '1'; end if; when update_output => debug_signal(3 downto 0) <= "1000"; debug_signal(7) <= debug_signal(7) xor '1'; -- LCD aktualisiert when others => debug_signal(3 downto 0) <= "0000"; end case; case state is ------

    in „Synthese macht nicht das selbe wie Simulation und "logische" Analyse“ · FPGA, VHDL & Co. ·

  • Datei

    pseuzufgen3.vhd

    B_COUNT + 1; -- Binärzähler wird inkrementiert end if; when "001" => QINT3 <= Q_OUT3; QINT2 <= (others => '0'); QINT4 <= (others => '0'); QINT5 <= (others => '0'); QINT8 <= (others => '0'); QINT16 <= (others => '0'); if QINT3 = "000" then QINT3(0) <= '1' after

    in „flexibler Pseudozufallszahlengenerator! was mache ich falsch?“ · FPGA, VHDL & Co. ·

  • Thread

    Beschreibung für eine Program

    " => reg_seg7 <= "1111100"; when "1100" => reg_seg7 <= "0111001"; when "1101" => reg_seg7 <= "1011110"; when "1110" => reg_seg7 <= "1111001"; when "1111" => reg_seg7 <= "1110001"; when others => reg_seg7 <= "XXXXXXX"; end case

    Also ich würde [vhdl] when others => reg_seg7 <= "XXXXXXX"; [/vhdl] erstmal durch [vhdl] when others => reg_seg7 <= "0000000"; [/vhdl] ersetzen. Denn einen undefinierten Zustand auf die Anzeige zu legen ist sicher nicht

    FPGA, VHDL & Co. ·Didi Lo · ·4 Antworten

  • Thread

    SDRAM mit Videobuffer für VGA Ausgabe

    END IF; ELSE VGA_VS<='1'; END IF; IF(XPOS>800 OR YPOS>600)THEN VGA_B<=(others=>'0'); VGA_G<=(others=>'0'); VGA_R<=(others=>'0'); END IF; IF(XPOS<752 AND YPOS<582)THEN-----visible img IF (READIMG='1')THEN CASE VB IS WHEN '0'=> VID_DATA<=VRAM_OUT2; WHEN '1' => VID_DATA<=VRAM_OUT1; WHEN OTHERS=>NULL; END CASE; IF(VGA_ADDR<751)THEN VGA_ADDR<=VGA_ADDR+1; END IF;

    FPGA, VHDL & Co. ·GS · ·1 Antworten

  • Datei

    Neuron.vhd

    others => Add_state <= idle; end case; end if; end process; with Add_Select_a select Add_a <= (others => '0') when "00", Mult_result when "01", (others => '0') when others; with Add_Select_b select Add_b <= (others => '0') when "00", Add_result when "01", (others => '0') when others; Output <= int_Output; Weight_Adr <= Layer_page & Layer_Input_Number; ready <= int_ready and not(execute); error <= Mult_underflow

    in „Pipeline MAC-Unit: Problem mit Latency“ · FPGA, VHDL & Co. ·

  • Datei

    video_generator.vhd

    -------- -- horizontal and vertical counters signal hcounter : std_logic_vector(10 downto 0) := (others => '0'); signal vcounter : std_logic_vector(10 downto 0) := (others => '0'); -- active when inside visible screen area. signal video_enable: std_logic; signal blank : std_logic; signal hs : std_logic

    in „LVDS Display per Spartan 6 ansteuern“ · FPGA, VHDL & Co. ·

  • Thread

    Probleme mit CASE Syntax

    der Fehler sein könnte. Code: mux: process (bram_adr) begin case bram_adr is when "000" => ram_1_wea <= '0'; Auch laut WIKI sollte das gehen: case din is when "00" => wert <= '1'; when others => null; end case; ModelSIM meldet aber: Enumeration literal

    Moin, Koennte ram_1_wea ein STD_LOGIC_VECTOR sein? Dann sollte also when "000" => ram_1_wea <= "0"; funktioniern. Gruss WK

    FPGA, VHDL & Co. ·Rolf · ·6 Antworten

  • Thread

    VHDL Grundlagen Tonerzeugung

    "000" when not "00100000" , "000" when others ; -- melody2 with sequencerStep select note2 <= "000" when not "00000001" , "010" when not "00000010" , "101" when not "00000100" , "011" when not "00001000" , "101" when not "00010000" , "010" when not "00100000" , "000" when others ; [/vhdl]

    FPGA, VHDL & Co. ·chris · ·123 Antworten

  • Thread

    VHDL Entprellung-Fehler

    -Hier steuert der Decoder bei bestimmten Eingangswertem die LED-Anzeigen an case c is when "0000" => hex <= "1000000"; when "0001" => hex <= "1111001"; when "0010" => hex <= "0100100"; when "0011" => hex <= "0110000"; when "0100" => hex <= "0011001"; when "0101" => hex <= "0010010"; when "0110" => hex <= "0000010"; when "0111" => hex <= "1111000"; when "1000" => hex <= "0000000"; when "1001" => hex <= "0010000"; when others => hex <= "1111111"; end case

    FPGA, VHDL & Co. ·Uwe_24 · ·18 Antworten

  • Datei

    i2s_shifter.vhdl

    (1); when "11" => bclk <= not bdiv_cnt (2); when others => NULL; end case; end process; process (bclk, res, data, adr, dwen) begin if res = '1' then data_l_temp <= (others => '0'); data_r_temp <= (others => '

    in „CPLD Programmieradapter“ · FPGA, VHDL & Co. ·

  • Thread

    LED-Blink VHDL

    count_nxt <= (others => '0'); state_nxt <= S_LED; end if; when S_LED => LEDG <= "1100"; state_NXT <= S_COUNT2; when S_COUNT2 => count_nxt <= count + to_unsigned(1, count'length); if

    count_nxt gemerkt werden (in einem LAtch). Ggf. braucht deine case-Struktur dann auch noch ein when others. Und ein Signal LEDG_nxt.

    FPGA, VHDL & Co. ·hans · ·8 Antworten

  • Thread

    Timing Requierement not met.Das System funktioniert nicht

    hab ich es gemacht: [vhdl] PROCESS(TD_CLK27) begin for i in 0 to 3 loop case i is when 0=> Datain<=TD_DATA; when 1=> BT656_Converter_IN<=Datain; when 2=> Raw_DATA<=BT656_Converter_OUT; when 3=> YCrCb_TO_RGB_IN<=Raw_Data; when 4=> RED_COMPONENT

    rising_edge(TD_CLK27)then BT656_ENABLE<='1'; if(VID_ENABLE='1')then CASE STATE IS WHEN GETCB=> validin<='0'; Comp_Cb<=BT656_DATA; STATE<=GETY; STATE_FLAG<='1'; WHEN GETCR=> IF(INIT='0')THEN validin<=

    FPGA, VHDL & Co. ·GS · ·12 Antworten

  • Datei

    dap_simple_synth.vhdl

    " => siBQ1CofB1S <= signed (siRWValue); when "00111" => siBQ1CofB2S <= signed (siRWValue); when "01000" => siBQ1CofB3S <= signed (siRWValue); when "01001" => siBQ1WrShadow <= '1'; when others => NULL; end case; else case siRReg is when "00000"

    in „Frage zu Optimierung“ · FPGA, VHDL & Co. ·