Suchergebnisse für "when others"

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898 Treffer für when others Suchergebnisse für "when others"

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  • Thread

    VHDL RAM Ansteuerung

    --------------- -- -- RamWrite Low --------------------------------------------- -- when Z6 => F_ZUSTAND <= Z0; -- ---------------------------------------------------------- -- -- Others---------------------------------------------------- -- when others => null;

    - In Abhängigkeit des Counters when 0 => IDATA(7 downto 0)<= DAT_IN; -- die Postions vergeben when 1 => IDATA(15 downto 8)<= DAT_IN; when 2 => IDATA(23 downto 16)<= DAT_IN; when others

    FPGA, VHDL & Co. ·Reni · ·4 Antworten

  • Thread

    Rechnen mit signed und unsigned

    end Broke; architecture verhalten of Broke is begin with cardsum select broke <= '1' when "10110", '1' when "10111", '1' when "11000", '1' when "11001", '1' when "11010", '1' when "11011", '1' when "11100", '1' when "11101", '1' when "11110", '1' when "11111", '0'when others; end verhalten; [/vhdl] Das ginge so viel kürzer: [vhdl] port( cardsum:in std_logic_vector(4 downto 0) broke

    FPGA, VHDL & Co. ·Anfänger · ·8 Antworten

  • Thread

    Process wird kontinuierlich durchloffen - Altium LiveDesign Board

    x"71" => usignal <= "1101"; zeichen <= '1'; -- ENTF(,) when x"66" => usignal <= "1110"; zeichen <= '1'; -- BACKSPACE when others => usignal <= "1111"; zeichen <= '1'; -- ERROR end case; else test <= '0'; END IF; END PROCESS; Process

    downto 0) <= wert1(3 downto 0); zustand <= x"03"; end if; when x"03" => zustand <= x"03"; when others => zustand <= x"FF"; -- ERROR end case; end if; end if; END Process; -- Ausgabe hier weggelassen end Behavioral; [/vhdl]

    FPGA, VHDL & Co. ·Daniel Schindler · ·34 Antworten

  • Thread

    Bitstrom per Huffman-Tabelle erzeugen

    when "11"=> rot_buffer(31 downto 24) <=input_reg(15 downto 8); when others=> null; end case; end if; end if; end if; end if; end process; process (barrel_pointer,rot_buffer)

    30 downto 15); when 31 => barrel<= rot_buffer (31 downto 16); when others => null; end case; end process; [/vhdl]

    FPGA, VHDL & Co. ·Cihan Kalayci · ·44 Antworten

  • Thread

    Problem mit LPT unter WinNT,Win200, WinXP

    -------------------- Configuration Register B, like Configuration Register A is only available when the ECP Port is in Configuration Mode. When in this mode, cnfgB resides at Base + 401h. Below is the make-up of the cnfgB Register. Bit(s) Function 7 1 Compress outgoing Data Using RLE 0 Do

    ports may be software configurable, where you can set the IRQ and DMA resources from the register. Others may be set via BIOS or by using jumpers on the Card, thus are read only. Bit 7 of the cnfgB Register selects whether to compress outgoing data using RLE (Run Length Encoding.) When Set, the host

    Softwareentwicklung ·Fix · ·39 Antworten

  • Thread

    SJA1000 ansteuern?

    Adresse begonnen wird) StateMachine := -1; -- Abarbeitung beenden when others => -- Zu allen anderen Zeitpunkten... null; -- ...nichts unternehmen end case; -- StateMachine

    Adresse begonnen wird) StateMachine := -1; -- Abarbeitung beenden when others => -- Zu allen anderen Zeitpunkten... null; -- ...nichts unternehmen end case; -- StateMachine

    FPGA, VHDL & Co. ·Steffen Hausinger · ·32 Antworten

  • Thread

    Asynchrone SRAM Controller mit Waitstate

    state_next <= rd1; end if; end if; ready <= '1'; when wr1 => state_next <= wr2; when wr2 => state_next <= idle; when rd1 => state_next <= rd2; when rd2=> data_s2f_next <=

    o for SRAM chip a ce_a_n <='0'; ub_a_n <='0'; lb_a_n <='0'; dio_a <= data_f2s_reg when tri_reg='0' else (others=>'Z'); end arch; Meine Frage lauten: 1) sieht mein SRAM Controller(FSM) funktionsfähig aus da ich nicht zum Laufen bringen konnte? 2) Wie soll ich dann 6 Waitstate

    FPGA, VHDL & Co. ·Keller Thomas · ·5 Antworten

  • Thread

    Hall Sensor in VHDL/FPGA

    when others => BCD_OUT <= "1110"; end case; end process; end arch; [/vhdl] [vhdl] LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BCD_TO

    "1000" => a <= '0'; b <= '0'; c <= '0'; d <= '0'; e <= '0'; f <= '0'; g <= '0'; when "1001" => a <= '0'; b <= '0'; c <= '0'; d <= '0'; e <= '1'; f <= '0'; g <= '0'; when others => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '1'; f <= '1'; g <= '0'; end case

    FPGA, VHDL & Co. ·Wolfgang · ·19 Antworten

  • Thread

    INOUT immer im 'U' Zustand

    std_logic := '1'; SIGNAL hlt: std_ulogic := '0'; SIGNAL dbus: std_logic_vector(7 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL rsel: std_logic_vector(4 DOWNTO 0) := (OTHERS => 'Z'); BEGIN u1: asic PORT MAP(reset, clk, cs, rd, wr, int, dbus, rsel); .... PROCEDURE ReadSCR(val: OUT byte

    Das [vhdl] clk <= '1' AFTER tcyc/2 WHEN (clk='0' AND hlt='0') ELSE '0' AFTER tcyc/2; [/vhdl] wäre so etwas kompakter und übersichtlicher: [vhdl] clk <= not clk AFTER tcyc/2 WHEN (hlt='0') ELSE '0'; [/vhdl] Aber sei's drum ;-)

    FPGA, VHDL & Co. ·Markus K. · ·18 Antworten

  • Thread

    Problem mit counter

    rechteck <= '0'; when "110" => rechteck <= '0'; when "111" => rechteck <= '0'; when others => end case; end process; ENTITY count IS PORT ( clock: IN STD_LOGIC; result: OUT

    Deine Statemaschine hat 9 Zustände. keine Ahnung, ich vermute mal, dass Du statt# when "111" => rechteck <= '0'; when others => end case; einfach when others => rechteck <= '0'; end case; schreiben solltest Gruß Kest

    FPGA, VHDL & Co. ·Mattias · ·7 Antworten

  • Thread

    Signalwertzuweisung zu spät

    0001"; elsif row_buttons_i <= "1111" then s_pressed_button <= (others => '0'); end if; when "1101" => if row_buttons_i(0) = '0' then s_pressed_button <= s_pressed_button or X"0004"; elsif

    2000"; elsif row_buttons_i <= "1111" then s_pressed_button <= (others => '0'); end if; when others => s_pressed_button <= (others => '0'); end case; end if; end if; end process; pressed_button_o

    FPGA, VHDL & Co. ·Johannes H. · ·5 Antworten

  • Thread

    Verilog Ausdruck "(| OOPS)" in VHDL

    Auswertung machen. Generisch würde man das in VHDL in etwa so schreiben: [vhdl] BACK_UP <= '1' when (OOPS != (others => '0')) and STATE = OOPS_S else '0'; [/vhdl] Gruß Marcus

    deinem VHDL Code muss ich dich leider berichtigen: Ungleich ist in VHDL "/=" nicht "!=", und (others => '0') darf nur bei einer Zuweisung verwendet werden, aber nicht bei einer Abfrage. Man könnte es dann so schreiben: [VHDL] BACK_UP <= '1' when (OOPS /= conv_std_logic_vector(0,OOPS'length

    FPGA, VHDL & Co. ·Guest · ·7 Antworten

  • Thread

    Multiplexer 5x2 in VHDL

    with s select y <= "00" when "000", "01" when "001", ... "11" when "111"; > Ich bekomme das einfach nicht auf die Kette. Du bist nur faul!

    with SEL select Y1 <= a(0) when "100", a(1) when "010", a(2) when "111", '0' when others; Y2 <= a(2) when "111", '0' when others; LED1 <= Y1; LED2 <= Y2;

    FPGA, VHDL & Co. ·Stefan M. · ·5 Antworten

  • Thread

    Bitfolge getriggert ausgeben

    std_logic_vector(63 downto 0) := x"1234567890abcdef"; signal sr_pattern : std_logic_vector(63 downto 0) : (others => '1'); signal sr_trigger : std_logic_vector(2 downto 0) : (others => '0'); : -- Trigger für Flankenerkennung einsynchronisieren sr_trigger <= sr_trigger(1 downto 0) & in_trigger when rising_edge

    Mark W. schrieb im Beitrag #5706996: > signal sr_pattern : std_logic_vector(63 downto 0) : (others => '1'); > signal trigger : std_logic : '0'; Ja, da fehlen wohl noch 2 '=' Zeichen. Aber keine Sorge, du findest den richtigen Platz. Einfach mal die Zeile drüber oder drunter anschauen... ;-)

    FPGA, VHDL & Co. ·Mark W. · ·17 Antworten

  • Thread

    Mittelwertbildung aus 16 16-Bit-Worten

    end if; end process; process (state) begin nextstate <= state; case state is when "00" => -- I2C-Bus Initialisieren ... when "01" => -- lesen vom I2C-Bus ... when "10" => -- MW-Bildung enable <= '1'; -- enable-signal für MW

    -- zuweisen nextstate <= "11"; end if; when "11" => -- senden auf I2C-Bus when others => nextstate <= "00"; end case; end process; Ich bin nun schon seit einigen Wochen dran und schaffe es einfach nicht. Es ist zum verzweifeln

    FPGA, VHDL & Co. ·Andi · ·15 Antworten

  • Thread

    mehere Archi/Entity

    ------------------- srctr_idle_p: process (state) begin case state is when FSM_IDLE|FSM_WRITE_MEM_3|FSM_READ_MEM_3 => srctr_idle_o <= '1'; --activate the idle-output signal when others => srctr_idle_o <= '0'; --deactivate the idle-output signal end

    ) <= to_stdlogicvector(data_reg(7 downto 0)); --transfer data_reg byte0 to mem_data_b byte1 when others => mem_data_b <= (others => 'Z'); --high impedance if not in Write-Mode end case; end process data_b_p ;

    FPGA, VHDL & Co. ·Crouch · ·1 Antworten

  • Thread

    signal zwar in simulation, aber nicht auf hardware

    hier mal ein auszug des codes: [vhdl] with ram_sw_i select wr_adr_a <= std_logic_vector(wr_adr_i) when '0', "00000" when others; with ram_sw_i select wr_adr_b <= std_logic_vector(wr_adr_i) when '1', "00000" when others; with ram_sw_i select wr_enable_a <= wr_en_i when '0', '0' when others; with ram_sw_i select wr_enable_b <= wr_en_i when '1', '0' when others; [/vhdl] jo ich kanns mir nicht erklären. es sollte ja eigentlich am pin anliegen. kann mir da jemand weiterhelfen? mfg Andi

    FPGA, VHDL & Co. ·Andi Z. · ·3 Antworten

  • Thread

    Ablauf von einer Programmänderung mit Quartus2

    begin if rising_edge(clk) then if terminal_count = '1' then case state is when "01" => state <= "10"; when "10" => state <= "01"; when others => state <= "01"; end case; end if; end if; end process

    case state is when "01" => state <= "10"; when "10" => state <= "01"; when others => state <= "01"; end case

    FPGA, VHDL & Co. ·Peter B. · ·8 Antworten

  • Thread

    VHDL-SPI implementierung

    Laenge --> alle Bits uebertragen signal tx_reg : std_logic_vector(Laenge-1 downto 0) := (others=>'0'); signal rx_reg : std_logic_vector(Laenge-1 downto 0) := (others=>'0'); begin ------ Verwaltung -------- process begin wait until rising_edge(CLK); MOSI <= tx_reg

    : : proces begin wait until rising_edge(clk); case state is when IDLE => if ... then : : state <= CALC; end if; when CALC => : : when READY => state <= IDLE; end

    FPGA, VHDL & Co. ·VHDL-Frage · ·26 Antworten

  • Thread

    UART + Xilinx + Altera

    tx_ready <= '0'; Tx <= '1'; case count_bit is when 0 => Tx <= '0'; count_bit <= count_bit + 1; when 9 => Tx <= '1'; count_bit <= count_bit + 1; when 10 => Tx <= '1'; count_bit <= 0; sent <= true; tx_ready <= '1'; when others => count_bit <= count_bit

    FPGA, VHDL & Co. ·Daniel R. · ·25 Antworten

  • Thread

    Multiplexer - SD Card - Richtung

    std_logic_vector (8 downto 0); data_ext: InOut std_logic_vector (8 downto 0); case select is when '1' => data_fpga<=data_sd; data_ext<= (others=>'Z'); -- hochohmig when '0' => data_fpga<=(others=>'Z'); -- hochohmig data_ext<= data_sd; end case; Danke

    Datenleitungen sind bidirektional, oder? Dann wäre das hier richtig: [vhdl] case select is when '1' => data_fpga<=data_sd; data_sd<=data_fpga; data_ext<= (others=>'Z'); -- hochohmig when '0' => data_fpga<=(others=>'Z'); -- hochohmig data_ext<= data_sd; data_sd

    FPGA, VHDL & Co. ·Nik Nn · ·11 Antworten

  • Thread

    Beschreibung für eine Program

    " => reg_seg7 <= "1111100"; when "1100" => reg_seg7 <= "0111001"; when "1101" => reg_seg7 <= "1011110"; when "1110" => reg_seg7 <= "1111001"; when "1111" => reg_seg7 <= "1110001"; when others => reg_seg7 <= "XXXXXXX"; end case

    Also ich würde [vhdl] when others => reg_seg7 <= "XXXXXXX"; [/vhdl] erstmal durch [vhdl] when others => reg_seg7 <= "0000000"; [/vhdl] ersetzen. Denn einen undefinierten Zustand auf die Anzeige zu legen ist sicher nicht

    FPGA, VHDL & Co. ·Didi Lo · ·4 Antworten

  • Thread

    SDRAM mit Videobuffer für VGA Ausgabe

    END IF; ELSE VGA_VS<='1'; END IF; IF(XPOS>800 OR YPOS>600)THEN VGA_B<=(others=>'0'); VGA_G<=(others=>'0'); VGA_R<=(others=>'0'); END IF; IF(XPOS<752 AND YPOS<582)THEN-----visible img IF (READIMG='1')THEN CASE VB IS WHEN '0'=> VID_DATA<=VRAM_OUT2; WHEN '1' => VID_DATA<=VRAM_OUT1; WHEN OTHERS=>NULL; END CASE; IF(VGA_ADDR<751)THEN VGA_ADDR<=VGA_ADDR+1; END IF;

    FPGA, VHDL & Co. ·GS · ·1 Antworten

  • Thread

    Probleme mit CASE Syntax

    der Fehler sein könnte. Code: mux: process (bram_adr) begin case bram_adr is when "000" => ram_1_wea <= '0'; Auch laut WIKI sollte das gehen: case din is when "00" => wert <= '1'; when others => null; end case; ModelSIM meldet aber: Enumeration literal

    Moin, Koennte ram_1_wea ein STD_LOGIC_VECTOR sein? Dann sollte also when "000" => ram_1_wea <= "0"; funktioniern. Gruss WK

    FPGA, VHDL & Co. ·Rolf · ·6 Antworten

  • Thread

    VHDL Grundlagen Tonerzeugung

    "000" when not "00100000" , "000" when others ; -- melody2 with sequencerStep select note2 <= "000" when not "00000001" , "010" when not "00000010" , "101" when not "00000100" , "011" when not "00001000" , "101" when not "00010000" , "010" when not "00100000" , "000" when others ; [/vhdl]

    FPGA, VHDL & Co. ·chris · ·123 Antworten

  • Thread

    VHDL Entprellung-Fehler

    -Hier steuert der Decoder bei bestimmten Eingangswertem die LED-Anzeigen an case c is when "0000" => hex <= "1000000"; when "0001" => hex <= "1111001"; when "0010" => hex <= "0100100"; when "0011" => hex <= "0110000"; when "0100" => hex <= "0011001"; when "0101" => hex <= "0010010"; when "0110" => hex <= "0000010"; when "0111" => hex <= "1111000"; when "1000" => hex <= "0000000"; when "1001" => hex <= "0010000"; when others => hex <= "1111111"; end case

    FPGA, VHDL & Co. ·Uwe_24 · ·18 Antworten

  • Thread

    LED-Blink VHDL

    count_nxt <= (others => '0'); state_nxt <= S_LED; end if; when S_LED => LEDG <= "1100"; state_NXT <= S_COUNT2; when S_COUNT2 => count_nxt <= count + to_unsigned(1, count'length); if

    count_nxt gemerkt werden (in einem LAtch). Ggf. braucht deine case-Struktur dann auch noch ein when others. Und ein Signal LEDG_nxt.

    FPGA, VHDL & Co. ·hans · ·8 Antworten

  • Thread

    Timing Requierement not met.Das System funktioniert nicht

    hab ich es gemacht: [vhdl] PROCESS(TD_CLK27) begin for i in 0 to 3 loop case i is when 0=> Datain<=TD_DATA; when 1=> BT656_Converter_IN<=Datain; when 2=> Raw_DATA<=BT656_Converter_OUT; when 3=> YCrCb_TO_RGB_IN<=Raw_Data; when 4=> RED_COMPONENT

    rising_edge(TD_CLK27)then BT656_ENABLE<='1'; if(VID_ENABLE='1')then CASE STATE IS WHEN GETCB=> validin<='0'; Comp_Cb<=BT656_DATA; STATE<=GETY; STATE_FLAG<='1'; WHEN GETCR=> IF(INIT='0')THEN validin<=

    FPGA, VHDL & Co. ·GS · ·12 Antworten

  • Thread

    Vereinfachung einer Beschreibung

    [vhdl] process(clk) begin wait until rising_edge(clk); case s is when a => if iEna='1' then s <= b; end if; when b => if iEna='0' then s <= a;

    myEna <= '1'; s <= c; end if; when c => if iEna='0' then s <= d; end if; when d => if other_ena='0' then s <= a; end if

    FPGA, VHDL & Co. ·Joe · ·8 Antworten

  • Thread

    FPGA Clockgenerierung

    clockCnt <= clockCnt + 1; --sonst counter erhöhen end if; when GLITCHING => if (clockCnt = definedGlitchCnt) then --dauer der glitche -> flanke oCLK <= not oCLK; clockCnt <= (others => '0');

    else clockCnt <= clockCnt + 1; --counter erhöhen end if; when POST_TRIGGER => if (clockCnt = definedClockCnt) then --normaler takt oCLK <= not oCLK; clockCnt <= (others => '0');

    FPGA, VHDL & Co. ·Igor · ·7 Antworten

  • Thread

    Frage zu variable counter : std_logic_vector(2 downto 0) := "100";

    when others => null; end case; counter := counter - 2; end if; -- zusammenfuehren der Kanaele: Es geht ein Schritt zurueck if counter <= "010" then case state is

    when others => null; end case; counter := counter + 2; end if; end process; end Behavioral; [/vhdl]

    FPGA, VHDL & Co. ·Reinhard J. · ·7 Antworten

  • Thread

    unsigned => hex

    "; when others => return "XXXX"; end case; end function;

    " & bin_in; when "1001" => shiftreg <= "100" & bin_in; when others => shiftreg <= shiftreg(2 downto 0) & bin_in; end case; end if; end if; end process; bcd_out <= shiftreg

    FPGA, VHDL & Co. ·Gast · ·5 Antworten

  • Thread

    Lockerer Counter auf VHDL

    architecture Behavioral of CounterMdl is signal tempNum: STD_LOGIC_VECTOR (Bits-1 downto 0) := (others => '0'); begin process(clk) begin if (clk='1' and clk'event) then tempNum <= tempNum + 1; output <= tempNum; end if; end process; end Behavioral; -------------

    architecture Behavioral of CounterMdl is > signal tempNum: STD_LOGIC_VECTOR (Bits-1 downto 0) := (others => '0'); > begin > process(clk) > begin > if (clk='1' and clk'event) then > tempNum <= tempNum + 1; > output <= tempNum; > end if; > end process; > end Behavioral

    FPGA, VHDL & Co. ·Samer Afach · ·18 Antworten

  • Thread

    Durch 10 teilen

    " when "0100", "1011011" when "0101", "1011111" when "0110", "1110010" when "0111", "1111111" when "1000", "1111011" when "1001", "0000000" when others; SEGA

    " when "0100", "1011011" when "0101", "1011111" when "0110", "1110010" when "0111", "1111111" when "1000", "1111011" when "1001", "0000000" when others; SEGA

    FPGA, VHDL & Co. ·Bastelboy · ·31 Antworten

  • Thread

    Uart Daten werden Falsch übertragen

    DataBitCnt_reg; data_next <= data_reg; rx_done_tick <='0'; case s_reg is when idle => if RXD='0' then s_next <= start; TickCnt_next <= (others=>'0'); end if; when start => if (RX_tick = '1') then if TickCnt_reg=7 then s_next <= data; TickCnt_next <= (others=>'0'); DataBitCnt_next <= (others=>'0'); else TickCnt_next <= TickCnt_reg + 1; end if; end if; when data

    FPGA, VHDL & Co. ·Maximilian S. · ·9 Antworten

  • Thread

    hexadezimalzahl drehung

    process( slv_reg_read_sel, slv_reg0 ) is begin case slv_reg_read_sel is when "1" => slv_ip2bus_data <= slv_reg0; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; ------------------------------------------

    IP to Bus signals ------------------------------------------ IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; end IMP;

    FPGA, VHDL & Co. ·reno kortes · ·4 Antworten

  • Thread

    Addition & Multiplikation mit FPGA

    when others => error <= '0'; zaehler <="000"; end case; end process; [/vhdl] MFG Falk

    zustand <= ZUSTAND_1; end if; ------------------------------------------ when others => NULL; end case; end if; end process; [/vhdl] Was hier klar sein muss, "zustand" und "led" werden als Register gebaut. Es sind damit Speicherelemente, die den Wert nur bei

    FPGA, VHDL & Co. ·D. E. · ·58 Antworten

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    State machine für SPI

    StateControl process. SIGNAL dataBuffer1, dataBuffer2 : STD_LOGIC_VECTOR(regBits-1 downto 0) := (others => '0'); SIGNAL temp : INTEGER := 0; -- states description: -- I defined here a Zero state as the state where both SPI_SCK and AD_CONV = 0. -- START_STATE: I wrote this

    are reset to avoid having latches, but not the one getting counted over in the current state when START_STATE => AD_CONV_WAIT_COUNTER_VAR := 0; SPI_CLK_EN_COUNTER_VAR := 0; DATA_AC1_COUNTER_VAR := 0; DATA_AC_WAIT_COUNTER_VAR := 0; DATA_AC2_COUNTER_VAR

    FPGA, VHDL & Co. ·Samer Afach · ·26 Antworten

  • Thread

    VHDL Newbie -->Kontrolle VHDL COde

    dabei ? Zeig doch mal, was du schon hast... Ich würde es mal so ansetzen: [vhdl] Latchout <= (others => '0') when (Reset = '1') else DB when (ADR7 = "00010100" AND IORQ = '0' AND WR = '0') else Latchout ; [/vhdl] BTW: hier im Forum kannst du mit den Tags [ vhdl ]

    <= (others => '0') when (Reset = '0') else -- DB when (ADR7 = "00010100" AND IORQ = '0' AND WR = '0') -- else Latchout ; CSROM <= MEMRD when ((ADR15="1110" OR ADR15="1111")

    FPGA, VHDL & Co. ·Ralph H. · ·23 Antworten

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    VHDL ROM Component: Sollte 1 geben, gibt aber X

    my_state <= write_back; when others => my_state <= halt; end case; when write_back => procouta <= accu; my_State <= advance_PC; when advance_PC => pc <= pc + 1; my_state <

    --Bestimem Op-Code case decodeOp(instruction(11 downto 8)) is when OP_OR => accu <= accu or getValue(instruction); my_state <= write_back; when others => my_state <= halt; end case; when write_back => procouta

    FPGA, VHDL & Co. ·Rene · ·7 Antworten

  • Thread

    VGA-Signal -Übertragungsprobleme.

    process; inScreen <= dispVertical and dispHorizontal; aktColumn <= aktHorizontal-144 when dispHorizontal='1' else 0; aktLine <= aktVertical-31 when dispVertical='1' else 0; Line <= aktLine; Column <= aktColumn; RedOut <= RedIn when inScreen='1' else '0'; GreenOut <= GreenIn when inScreen='1' else '0'; BlueOut <= BlueIn when inScreen='1' else '0'; Hsync <= syncH; Vsync <= syncV; end Behavioral; [/vhdl]

    FPGA, VHDL & Co. ·Mike · ·12 Antworten

  • Thread

    FF/Latch Warnung bei LCD Display

    Effekte beobachten: [vhdl] --multiplexer richtig schalten with AKT_STATUS select SCHALT <= '1' when INIT, '0' when others; with SCHALT select LCD_E <= LCD_E0 when '0', --zum übertragen LCD_E1 when others; --zum Initialisieren --gibt Aufschluss darüber, ob Daten oder Befehle übertragen werden --RS=0 für Befehle und RS=1 für Daten with AKT_STATUS select LCD_RS <= '0' when FUNCTION_SET| ENTRY_SET | SET_DISPLAY |CLEAR_DISPLAY |SET_ADDR, '1' when others; [/vhdl] Denn die Umschaltung zwischen den Zuständen geschieht nicht in 0.0ns, sondern es dauert dank Laufzeiten und

    FPGA, VHDL & Co. ·Johannes · ·43 Antworten

  • Thread

    bleibe in Zustand hängen, warum?

    when "10111" => FOLGE_Z <= Z_LEFT; when "01111" => FOLGE_Z <= Z_RIGHT; when others => FOLGE_Z <= Z0; end case; when Z_UP => FOLGE_Z <= Z

    when "11011" => FOLGE_Z <= Z_DOWN; when "10111" => FOLGE_Z <= Z_LEFT; when "01111" => FOLGE_Z <= Z_RIGHT; when others => FOLGE_Z <= Z0;

    FPGA, VHDL & Co. ·Ole · ·11 Antworten

  • Thread

    VHDL Problem mit IF

    probiers mal mit einem case statment in der clock also if rising_edge(clk) then case xy is when "0000" => r<='1'; when "" => when others => end case; end if;

    g<='0'; end if; when others => end case; end if; /vhdl

    FPGA, VHDL & Co. ·Kaffeetasse · ·15 Antworten

  • Thread

    Zaehler so langsam?

    FULL <= '0'; -- clear full flag end if; when others => adress_cnt <= adress_cnt + 1; -- no overflow increase adress_cnt end case; end if; end if; end if; end

    "; DOUT <= DIN(95 downto 88); when others => ramenable_int <= "000000000000"; DOUT <= DIN(7 downto 0); end case; end if; end if; end process; end RTL; [/vhdl] Dirk

    FPGA, VHDL & Co. ·Dirk · ·24 Antworten

  • Thread

    VHDL Codeergänzung um Pushbutton zu entprellen

    "0100100" when "0101", -- 5 "0100000" when "0110", -- 6 "0001111" when "0111", -- 7 "0000000" when "1000", -- 8 "0000100" when "1001", -- 9

    "0111000" when "1111", -- F "1111111" when others; -- turn off all LED ausgang_anode <= "1110"; --clk_proc: process(clk, reset) clk_proc: process(clk, reset, taster) begin

    FPGA, VHDL & Co. ·Tob M. · ·4 Antworten

  • Thread

    Entfernen von Spikes ohne Eintakten

    Zählerstandes end if; end process; with counter_i select reset_enable_i <= '0' when "0000000000", '1' when others;[/vhdl] meine zielplattform ist ein lattice machxo 2280C. ich habe meine asynchronen I2S signale alle 2mal eingetaktet. der takt TXC läuft mit 25 MHz

    Systemtakt? Woher kommt der TXC? BTW: [vhdl] with counter_i select reset_enable_i <= '0' when "0000000000", '1' when others; [/vhdl] Das könntest du leserlicher so schreiben: [vhdl] reset_enable_i <= '0' when counter_i="0000000000" else '1'; [/vhdl] Und auch das sieht sehr

    FPGA, VHDL & Co. ·Andi Z. · ·15 Antworten

  • Thread

    Unterschied von selektiven Signalzuweisungen und cases in Prozessen

    Was ist eigentlich der Unterschied zwischen [vhdl] with mode select signal1 <= signal1a when modeA, signal1b when modeB, signal1c when modeC; with mode select signal2 <= signal2a when modeA, signal2b when modeB, signal2c when modeC; [/vhdl] und [vhdl] process (mode, signal1a, signal1b, signal1c, signal2a, signal2b, signal2c ) begin case mode is when modeA =>

    FPGA, VHDL & Co. ·Andreas D. · ·4 Antworten

  • Thread

    UART empfangen auf FPGA

    when "0100" => TXD <= S_OUTPUT_BUFFER(3); when "0101" => TXD <= S_OUTPUT_BUFFER(4); when "0110" => TXD <= S_OUTPUT_BUFFER(5); when "0111" => TXD <= S_OUTPUT_BUFFER(6); when "1000" => TXD <= S_OUTPUT_BUFFER(7); when "1001" => TXD <= '1'; when others => NULL; end case; else TXD <= '1'; end if; end if

    FPGA, VHDL & Co. ·Hans Hirsch · ·42 Antworten

  • Thread

    Statemaschine fehler!

    ; when ras2 => usb_next_stat <= ras3; when ras3 => usb_next_stat <= ras4; when ras4 => usb_next_stat <= ras5; when ras5 => usb_next_stat <= idle; when others => usb_next_stat

    <= ras2; when ras2 => usb_next_stat <= ras3; when ras3 => usb_next_stat <= ras4; when ras4 => usb_next_stat <= ras5; when ras5 => usb_next_stat <= idle; when others => usb_next_stat

    FPGA, VHDL & Co. ·Frank Stucke · ·12 Antworten